XC2C32A-4CP56C vs XC2C32A-6CP56C Comparaison
Comparaison détaillée côte à côte de XC2C32A-4CP56C par AMD et XC2C32A-6CP56C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC2C32A-4CP56C | XC2C32A-6CP56C |
|---|---|---|
| Marque | AMD | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Device Type | CoolRunner-II complex programmable logic device | CoolRunner-II complex programmable logic device (CPLD) |
| Macrocells | 32 macrocells | — |
| Internal Frequency | 450 MHz | 450 MHz |
| Propagation Delay | 3.8 ns | 4 ns |
| Maximum Pin-to-Pin Logic Delay | 3.0 ns | — |
| User I/Os | 33 pins | — |
| Total Pins | 56 pins | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Courant de repos | 12 µA minimum | 12 µA |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS |
| Logic Family | CMOS | CMOS |
| Boîtier | 56-pin CSPBGA, 6 x 6 mm, 0.50 mm pitch | CSP-56, 6 x 6 mm, 0.50 mm pitch |
| Terminal Type | Ball | — |
| Package Shape | Square | — |
| Temperature Grade | Commercial | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | Lead Free | — |
| Programming Interface | [DATA_NEEDED: programming interface details] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Macrocell Count | — | 32 macrocells |
| Logic Gate Count | — | 750 gates |
| User I/O Count | — | 33 pins |
| Logic Array Blocks | — | 2 logic array blocks |
| Maximum Operating Frequency | — | 200 MHz |
| Minimum Pin-to-Pin Logic Delay | — | 3.0 ns |
| Internal Supply Voltage Range | — | 1.7 V to 1.9 V |
| Total Package Pins | — | 56 balls |
| Type de montage | — | Surface mount |
| Programming Support | — | In-system programmable |
| REACH Status | — | [DATA_NEEDED: REACH status] |