XC2C32A-4CP56C vs XC2C32A-6CP56C 对比

详细并排对比 XC2C32A-4CP56C 出自 AMD 和 XC2C32A-6CP56C 出自 Xilinx。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Xilinx
XC2C32A-6CP56C XC2C32A-6CP56C - 32-Macrocell 200MHz CPLD | Xilinx

XC2C32A-6CP56C - 32-Macrocell 200MHz CPLD | Xilinx

XC2C32A-6CP56C ✓ 量产中

规格对比

参数 XC2C32A-4CP56C XC2C32A-6CP56C
品牌 AMD Xilinx
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
Device Type CoolRunner-II complex programmable logic device CoolRunner-II complex programmable logic device (CPLD)
Macrocells 32 macrocells —
Internal Frequency 450 MHz 450 MHz
Propagation Delay 3.8 ns 4 ns
Maximum Pin-to-Pin Logic Delay 3.0 ns —
User I/Os 33 pins —
Total Pins 56 pins —
Core Supply Voltage 1.8 V 1.8 V
静态电流 12 µA minimum 12 µA
Process Technology 0.18 µm CMOS 0.18 µm CMOS
Logic Family CMOS CMOS
封装 56-pin CSPBGA, 6 x 6 mm, 0.50 mm pitch CSP-56, 6 x 6 mm, 0.50 mm pitch
Terminal Type Ball —
Package Shape Square —
Temperature Grade Commercial —
RoHS 状态 Compliant [DATA_NEEDED: RoHS status]
Lead-Free Status Lead Free —
Programming Interface [DATA_NEEDED: programming interface details] —
工作温度范围 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Macrocell Count — 32 macrocells
Logic Gate Count — 750 gates
User I/O Count — 33 pins
Logic Array Blocks — 2 logic array blocks
Maximum Operating Frequency — 200 MHz
Minimum Pin-to-Pin Logic Delay — 3.0 ns
Internal Supply Voltage Range — 1.7 V to 1.9 V
Total Package Pins — 56 balls
安装类型 — Surface mount
Programming Support — In-system programmable
REACH Status — [DATA_NEEDED: REACH status]

数据手册与资源

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