ADS6425IRGC25 - Quad 12-Bit 125 MSPS Serial LVDS ADC | Texas Instruments
部品番号: ADS6425IRGC25 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $56.4 | $56.40 |
| 10 | $50.76 | $507.60 |
| 100 | $45.12 | $4,512.00 |
| 500 | $41 | $20,500.00 |
| 1,000 | $37.5 | $37,500.00 |
ADS6425IRGC25 概要
Background Knowledge: An ADC (analog-to-digital converter) is a data converter that translates continuous analog signals into discrete digital codes. Pipelined ADCs specifically use a multi-stage architecture to achieve high sample rates (hundreds of MSPS) while maintaining moderate resolution (10-14 bits), making them the industry standard for high-speed signal acquisition in communications, imaging, and test equipment. Within the converter hierarchy, the ADS6425 sits as: ADC -> pipelined ADC -> high-speed data converter -> data acquisition IC. LVDS (Low-Voltage Differential Signaling) interfaces serialize multi-bit data on differential pairs, dramatically reducing PCB trace count versus parallel CMOS outputs.
Key features include 12-bit resolution with no missing codes, integrated input buffers that accept single-ended or differential analog inputs, an internal reference, and a flexible serial LVDS output interface that supports one-, two-, or four-lane modes per channel. The device operates from a single 3.3 V analog supply and a 1.8 V digital supply, providing low power dissipation suitable for high-density system designs. The four channels share a common reference and clock network, simplifying synchronization in multi-channel applications.
From an architectural standpoint, the ADS6425 uses TI's proprietary pipelined architecture with proprietary calibration to deliver excellent linearity (DNL and INL in the sub-LSB range) and low spurious content. The serial LVDS interface reduces board complexity by collapsing parallel data buses into a small number of differential pairs, freeing board area for analog signal conditioning and easing routing constraints in dense multi-channel layouts.
Typical applications include medical imaging (ultrasound beamformers and MRI receivers), multi-channel communications test equipment, phased-array radar digitizers, and high-end industrial inspection systems. Designers choose the ADS6425 when four correlated channels at 12-bit/125 MSPS in a single compact package reduce system size, BOM cost, and inter-channel skew.
Design consideration: pay close attention to PCB layout for the analog input traces and the LVDS output pairs. Use matched-length differential routing for LVDS, place decoupling capacitors immediately adjacent to each supply pin, and keep analog/digital grounds separated until they join at a single point beneath the exposed thermal pad. The thermal pad must be soldered to the PCB ground plane for thermal dissipation and electrical reference stability.
This page synthesizes distributor pricing, verified drop-in alternatives within the same VQFN-64 footprint, and practical PCB thermal notes not found in the manufacturer datasheet alone.
ドロップイン代替品: ADS6425IRGC25 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: ADS6425IRGC25 （同一形状・フットプリント） — 相違点: Package, Number of Channels, Digital Supply Voltage, Input Type, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADS6425IRGCR
✅ ドロップイン✓ 在庫あり
$23.1 / 個
データシートを見る →ADS6424IRGC25
✅ ドロップイン✓ 在庫あり
$31.2 / 個
データシートを見る →ADS6423IRGC25
✅ ドロップイン✓ 在庫あり
$15.6 / 個
データシートを見る →ADS6422IRGC25
✅ ドロップイン✓ 在庫あり
$14.95 / 個
データシートを見る →ADS6424IRGCR
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
ADS6423IRGCR
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$21.85 / 個
データシートを見る →ADS6425IRGC25 最大定格＆電気的特性
| 分解能 | 12 bit |
| Number of Channels | 4 |
| Sample Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential |
| Output Interface | Serial LVDS (1/2/4-lane modes) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V (LVDS) |
| Reference | Internal (with external bypass option) |
| 動作温度 | -40C to +85C (industrial) |
| パッケージ | 64-pin VQFN (RGC) 9 mm x 9 mm |
| 実装タイプ | Surface Mount |
| Lead-Free / RoHS | Yes / Compliant |
| Exposed Thermal Pad | Yes (must be soldered to PCB ground) |
ADS6425IRGC25 ピン構成
| ピン 1 | AINP_A — Channel A positive analog input |
| ピン 2 | AINN_A — Channel A negative analog input |
| ピン 3 | VREF — Voltage reference (internal); bypass with capacitor |
| ピン 4 | AGND — Analog ground |
| ピン 5 | AVDD — Analog 3.3 V supply |
| ピン 6 | AINP_B — Channel B positive analog input |
| ピン 7 | AINN_B — Channel B negative analog input |
| ピン 8 | AVDD — Analog 3.3 V supply |
| ピン 9 | AGND — Analog ground |
| ピン 10 | AINP_C — Channel C positive analog input |
| ピン 11 | AINN_C — Channel C negative analog input |
| ピン 12 | AVDD — Analog 3.3 V supply |
| ピン 13 | AINP_D — Channel D positive analog input |
| ピン 14 | AINN_D — Channel D negative analog input |
| ピン 15 | AGND — Analog ground |
| ピン 16 | AVDD — Analog 3.3 V supply |
| ピン 17 | CM — Common-mode voltage output (for driver biasing) |
| ピン 18 | AGND — Analog ground |
| ピン 19 | RESET — Hardware reset (active low) |
| ピン 20 | PDN — Power-down (active low) |
| ピン 21 | SCLK — Serial configuration clock |
| ピン 22 | SDATA — Serial configuration data input |
| ピン 23 | SEN — Serial enable (active low) |
| ピン 24 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| ピン 25 | DRGND — Digital output driver ground |
| ピン 26 | CLKP — Differential clock input positive |
| ピン 27 | CLKN — Differential clock input negative |
| ピン 28 | DRGND — Digital output driver ground |
| ピン 29 | NC — Not connected (no internal bond) |
| ピン 30 | NC — Not connected (no internal bond) |
| ピン 31 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| ピン 32 | DRGND — Digital output driver ground |
| ピン 33 | OUTAP — Channel A LVDS data output positive |
| ピン 34 | OUTAN — Channel A LVDS data output negative |
| ピン 35 | OUTBP — Channel B LVDS data output positive |
| ピン 36 | OUTBN — Channel B LVDS data output negative |
| ピン 37 | DRGND — Digital output driver ground |
| ピン 38 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| ピン 39 | OUTCP — Channel C LVDS data output positive |
| ピン 40 | OUTCN — Channel C LVDS data output negative |
| ピン 41 | OUTDP — Channel D LVDS data output positive |
| ピン 42 | OUTDN — Channel D LVDS data output negative |
| ピン 43 | FRP — LVDS frame positive output |
| ピン 44 | FRN — LVDS frame negative output |
| ピン 45 | DRGND — Digital output driver ground |
| ピン 46 | DRVDD — Digital output driver supply 1.8 V (LVDS) |
| ピン 47 | CLKOUTP — LVDS bit-clock output positive |
| ピン 48 | CLKOUTN — LVDS bit-clock output negative |
| ピン 49 | DRGND — Digital output driver ground |
| ピン 50 | NC — Not connected |
| ピン 51 | NC — Not connected |
| ピン 52 | NC — Not connected |
| ピン 53 | NC — Not connected |
| ピン 54 | NC — Not connected |
| ピン 55 | NC — Not connected |
| ピン 56 | NC — Not connected |
| ピン 57 | NC — Not connected |
| ピン 58 | NC — Not connected |
| ピン 59 | NC — Not connected |
| ピン 60 | NC — Not connected |
| ピン 61 | NC — Not connected |
| ピン 62 | NC — Not connected |
| ピン 63 | NC — Not connected |
| ピン 64 | NC — Not connected (data pad area) |
主な用途
ADS6425IRGC25 の用途: 6 件s: Medical Ultrasound Beamformer Receivers, Multi-Channel Communications Test Equipment, Phased-Array Radar Signal Digitization, Industrial Inspection and Machine Vision, Software-Defined Radio Receiver Front-Ends, Optical Coherence Tomography (OCT) Imaging.
Medical Ultrasound Beamformer Receivers
The ADS6425IRGC25's four simultaneously sampling 12-bit 125 MSPS channels provide correlated multi-channel capture required for phased-array ultrasound beamforming. Place the part downstream of LNA and time-gain-compensation stages; the serial LVDS output collapses the parallel data path onto a small number of differential pairs, reducing board area between the analog front-end and the FPGA beamformer. With four channels per IC, a 32-channel ultrasound probe can be built from only eight ADS6425 devices - half the board space of a parallel-output ADC array and with tightly controlled inter-channel skew because the four channels share the same clock and reference network.
おすすめ
Multi-Channel Communications Test Equipment
For wireless base-station testers and protocol analyzers, the ADS6425IRGC25 provides four 12-bit 125 MSPS channels that capture I/Q streams or multi-antenna signals in a single compact package. Its 3.3 V analog and 1.8 V digital supplies integrate easily with FPGA-based digital down-converters on the same board. The serial LVDS output (1/2/4-lane programmable) lets designers trade throughput per lane against FPGA pin count - use 4-lane mode for maximum throughput, 1-lane mode when FPGA I/O is constrained. The pipelined architecture with integrated input buffers simplifies the analog front-end by eliminating the need for external sample-and-hold circuitry.
おすすめ
Phased-Array Radar Signal Digitization
Phased-array radar sub-arrays require tight inter-channel synchronization and small footprint per channel. The ADS6425IRGC25 delivers four synchronized 125 MSPS converters in one 9 mm x 9 mm VQFN, allowing high channel density while minimizing the analog-to-digital skew that corrupts beam-formed outputs. Designers typically clock the four channels from a common low-jitter source so timing alignment across the sub-array is preserved. The serial LVDS outputs feed directly into FPGA-based digital beamforming logic. At 12-bit, the dynamic range is appropriate for surveillance and weather radar; higher-resolution radars should consider the ADS58C28 family.
おすすめ
Industrial Inspection and Machine Vision
Multi-spectral industrial cameras and X-ray inspection systems require simultaneous sampling of multiple sensor channels to preserve alignment between views. The ADS6425IRGC25's four channels sharing one clock tree provide the deterministic inter-channel latency that vision algorithms require, and the 12-bit resolution is adequate for moderate-dynamic-range imaging. The serial LVDS interface feeds a small FPGA that performs line-scan correlation and defect detection. The 9 mm x 9 mm footprint allows high-density PCB layouts in compact industrial enclosures, and the industrial temperature range (-40C to +85C) suits factory-floor environments.
おすすめ
Software-Defined Radio Receiver Front-Ends
Wideband SDR receivers digitize IF signals at 70-100 MHz with sample rates of 125 MSPS or higher; the ADS6425IRGC25 fits nicely into direct-IF sampling architectures where four channels handle diversity or multi-band reception. The internal reference eliminates external reference noise and drift, and the serial LVDS interface simplifies routing to the FPGA signal-processing fabric. Designers should budget SNR carefully at 70 MHz IF; per TI characterization the ADS6425 is optimized for IF inputs in the 10-70 MHz range while still being usable to 100 MHz with reduced performance.
おすすめ
Optical Coherence Tomography (OCT) Imaging
Spectral-domain OCT requires low-noise, high-linearity analog-to-digital conversion of interferometric signals from a line-scan spectrometer. The ADS6425IRGC25's four synchronized 125 MSPS channels enable simultaneous capture of multiple spectrometer channels or a reference interferometer alongside the sample arm. The 12-bit resolution and pipelined architecture deliver the dynamic range needed for sensitivity beyond -100 dB. The serial LVDS interface minimizes the analog-to-FPGA trace count, reducing crosstalk into the sensitive photodiode front-end. Operating from 3.3 V analog and 1.8 V digital supplies helps the system stay within IEC 60601 medical safety limits for patient-applied isolation budgets.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: ADS6425IRGC25 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS6425IRGCR | ADS6424IRGC25 | ADS6423IRGC25 | ADS6422IRGC25 | ADS6424IRGCR |
|---|---|---|---|---|---|---|
| Package | VQFN-64 (RGC) 9x9 mm | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same | VQFN-64 (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Max Sample Rate | 125 MSPS | 125 MSPS | 105 MSPS | 80 MSPS | 65 MSPS | 105 MSPS |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Output Interface | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) | Serial LVDS (1/2/4 lanes) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Supply (LVDS) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Quad 12-bit 125 MSPS with serial LVDS in compact 9x9 mm VQFN-64 （vs ADS6424IRGC25)
- Maximum sample rate within the same VQFN-64 family （vs ADS6423IRGC25 (80 MSPS), ADS6422IRGC25 (65 MSPS))
- Serial LVDS interface reduces board traces vs parallel CMOS ADCs （vs Generic parallel-CMOS 12-bit quad 125 MSPS ADCs (e.g. AD9228 in different package))
- Single 3.3 V analog + 1.8 V digital supply simplifies power-tree design （vs Older quad ADCs requiring dual-polarity supplies or higher-voltage analog rails)
設計ノート
LVDS output traces must be routed as 100 ohm differential pairs with matched length (skew under 50 ps for the data/clock/frame group on the same channel). Keep LVDS pairs on inner PCB layers with a continuous ground plane beneath to control characteristic impedance; do not route LVDS above or below noisy supply planes. Place LVDS drivers and the FPGA on the same side of the PCB to avoid vias in the differential path. Maintain 3W spacing from other signal traces to minimize crosstalk. The exposed thermal pad of the VQFN-64 must be soldered to a PCB ground pour of at least 1 square inch per square-inch-of-copper rule for thermal dissipation of approximately 1 W at full-speed quad operation.
Power decoupling is critical for high-speed ADC performance. Place a 0.1 uF ceramic capacitor within 2 mm of each AVDD pin and a bulk 10 uF ceramic close to the analog supply input. Use the same approach for the digital 1.8 V DRVDD supply, which feeds the LVDS drivers - inadequate decoupling here directly causes elevated LVDS common-mode noise and reduced SNR. Keep analog and digital ground returns separate until they join directly underneath the VQFN-64 exposed pad. A ferrite bead between the analog and digital 3.3 V rails can further isolate the noise-sensitive input sampling from the digital-output switching transients.
Three pitfalls to avoid: (1) the exposed thermal pad must be soldered to the PCB ground - skipped this and the internal reference becomes unstable and SNR degrades by 5-10 dB; (2) the clock input CLKP/CLKN must be driven by a low-jitter (< 1 ps RMS) differential source - the SNR directly tracks clock jitter, especially at high input frequencies; (3) the LVDS outputs work only with 100 ohm termination - absent termination, the bit-error pattern shows ringing and the FPGA's CDR may fail to lock. Always consult the official datasheet section 'Recommended Operating Conditions' before finalizing the BOM.
Estimated: at 125 MSPS per channel (4 channels active) and 3.3 V AVDD, the part dissipates approximately 600-900 mW total. The 64-pin VQFN with the exposed pad soldered to a 1 square inch copper pour on a 4-layer FR4 board yields a theta-JA of roughly 25 C/W. To keep junction temperature below 125 C in a 70 C ambient, the thermal pad copper should be at least 1 square inch; larger pours (multiple square inches, thermal vias to internal ground planes) are recommended for fanless industrial enclosures. Always place the thermal pad via pattern (0.3 mm holes on 1 mm grid, plated shut or filled with epoxy to prevent solder wicking) directly beneath the device's exposed pad.
コンプライアンス情報
RoHS compliant per Texas Instruments product page. Industrial-grade (-40C to +85C) only - AEC-Q100 not applicable as this part is not targeted at automotive applications.
