AT28C010-12JC - 1Mb Parallel EEPROM 120ns | Microchip | 32-PLCC
Référence : AT28C010-12JC ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $39.13 | $39,13 |
| 10 | $35.2 | $352,00 |
| 100 | $28.5 | $2 850,00 |
| 500 | $24.75 | $12 375,00 |
| 1 000 | $21.9 | $21 900,00 |
AT28C010-12JC Présentation
A parallel EEPROM is a non-volatile memory class that allows byte- or page-level electrical erase and rewrite while preserving the fast random-access read characteristics of static RAM. Within the broader semiconductor hierarchy, the AT28C010-12JC sits as: EEPROM -> non-volatile memory (NVM) -> memory IC -> integrated circuit -> semiconductor. EEPROMs fill the niche between mask ROM (one-time programmable, lowest cost) and battery-backed SRAM (byte-write, but volatile on power loss), offering unlimited endurance cycles with no battery requirement at the cost of higher per-bit price.
Key features include an internal 128-byte page register that enables simultaneous writing of up to 128 bytes with a 10 ms page-write cycle, automatic erase-before-write using on-chip latches, and built-in Data Protection (the AT28C010 requires an active-high +5V WR pulse, eliminating accidental write conditions). The device is available in commercial (0C to +70C) and industrial (-40C to +85C) temperature ranges, with military (-55C to +125C) screening on selected variants.
The architecture uses a paged CMOS cell array with on-chip address and data latches driven by standard JEDEC-equivalent microprocessor bus timing; OE, CE, and WE control signals deliver SRAM-like interface simplicity. Power dissipation falls to 0.35 mW in CMOS standby, an order of magnitude below TTL-active standby, extending battery-backed retention profiles for systems that idle between writes.
Typical applications include firmware program storage in legacy 8-bit MCU subsystems (8051, 68HC11), configuration parameter retention in industrial PLCs, VXI/PXI instrument calibration tables, point-of-sale (POS) terminal transaction logging, and military/aerospace equipment requiring MIL-STD-883 screening. Its wide operating temperature and paged-write architecture also suit avionics data recorders and ruggedized field instrumentation.
Designers should treat PLCC pin 1 orientation carefully and observe strict Vcc decoupling near the package to avoid write-disturbance. The 32-PLCC footprint is JEDEC-standard; legacy PCBs designed around the 32-pin DIP AT28C010 can be migrated by adding a low-profile PLCC socket without any PCB rework.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour AT28C010-12JC — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
AT28C010-12JI
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
AT28C010E-12JC
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
AT28C010-15JC
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
AT28C010-10JC
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
AT28C010-12JC Valeurs maximales et caractéristiques électriques
| Type de mémoire | Parallel EEPROM (Electrically Erasable Programmable ROM) |
| Taille de mémoire | 1 Mbit |
| Organisation de la mémoire | 128K x 8 |
| Access Time | 120 ns (maximum) |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V |
| Température de fonctionnement | 0 C to +70 C (commercial, JC suffix) |
| Type d'interface | Parallel (SRAM-like JEDEC bus) |
| Page Size | 128 bytes |
| Page Write Cycle Time | 10 ms (maximum) |
| Active Power Dissipation | 220 mW (maximum) |
| Package Type | 32-PLCC (Plastic Leaded Chip Carrier), JEDEC-standard |
| Package Dimensions | 13.97 mm x 11.43 mm |
| Type de montage | Surface Mount (PLCC socket recommended) |
| Write Protection | Data Protection latch (Vcc-only write, accidental-write immune) |
Configuration des broches de AT28C010-12JC
| Broche 1 | NC — No connect (reserved per datasheet) |
| Broche 2 | A16 — Address input bit 16 (MSB) |
| Broche 3 | A14 — Address input bit 14 |
| Broche 4 | A12 — Address input bit 12 |
| Broche 5 | A7 — Address input bit 7 |
| Broche 6 | A6 — Address input bit 6 |
| Broche 7 | A5 — Address input bit 5 |
| Broche 8 | A4 — Address input bit 4 |
| Broche 9 | A3 — Address input bit 3 |
| Broche 10 | A2 — Address input bit 2 |
| Broche 11 | A1 — Address input bit 1 |
| Broche 12 | A0 — Address input bit 0 (LSB) |
| Broche 13 | I/O0 — Bidirectional data bit 0 (LSB) |
| Broche 14 | I/O1 — Bidirectional data bit 1 |
| Broche 15 | I/O2 — Bidirectional data bit 2 |
| Broche 16 | GND — Ground (Vss) |
| Broche 17 | I/O3 — Bidirectional data bit 3 |
| Broche 18 | I/O4 — Bidirectional data bit 4 |
| Broche 19 | I/O5 — Bidirectional data bit 5 |
| Broche 20 | I/O6 — Bidirectional data bit 6 |
| Broche 21 | I/O7 — Bidirectional data bit 7 (MSB) |
| Broche 22 | CE — Chip Enable (active low) |
| Broche 23 | A10 — Address input bit 10 |
| Broche 24 | OE — Output Enable (active low) |
| Broche 25 | A11 — Address input bit 11 |
| Broche 26 | A9 — Address input bit 9 |
| Broche 27 | A8 — Address input bit 8 |
| Broche 28 | A13 — Address input bit 13 |
| Broche 29 | WE — Write Enable (active low) |
| Broche 30 | A15 — Address input bit 15 |
| Broche 31 | NC — No connect (reserved per datasheet) |
| Broche 32 | VCC — +5V power supply input |
Applications typiques
AT28C010-12JC convient pour 6 applications: Embedded Firmware Storage for 8051/68HC11 MCUs, Industrial PLC Configuration Parameter Storage, VXI/PXI Test & Measurement Calibration Tables, Point-of-Sale (POS) Terminal Transaction Logging, Avionics & Military Data Recorders, Legacy Industrial Controller Firmware Replacement.
Embedded Firmware Storage for 8051/68HC11 MCUs
The AT28C010-12JC provides reliable 1 Mbit program storage for 8-bit microcontroller subsystems where in-system programming and field updates are required. Its 120 ns access time pairs well with 8 MHz 8051 derivatives without wait-state insertion, and the 128-byte paged write enables fast block updates of bootloader or firmware revision tables. Place Vcc decoupling (0.1 uF) within 5 mm of pin 32, route OE and WE with matched trace lengths, and use the on-chip Data Protection latch to prevent accidental reprogramming during brownouts or power glitches.
Recommandé
Industrial PLC Configuration Parameter Storage
In programmable logic controllers, the AT28C010-12JC retains calibration constants, set-point tables, and ladder-logic revisions across power cycles. The 1 Mbit density accommodates rich look-up tables for PID tuning and recipe storage in food/pharma batch controllers. Its 220 mW active dissipation fits within the thermal budget of sealed IP65 enclosures, while the 10 ms page-write time is acceptable for non-real-time configuration tasks. Designing with the AT28C010-12JC for PLC use typically pairs it with a supervisor (e.g. MAX1232) for clean POR sequencing.
Recommandé
VXI/PXI Test & Measurement Calibration Tables
Calibration coefficients, linearity correction vectors, and serial-number inventory for VXI/PXI instruments fit naturally into the AT28C010-12JC's 128K x 8 organization. The 120 ns access allows instrument firmware to read correction data without wait states at typical 8-16 MHz bus speeds, and the byte-writeability allows per-channel field calibration updates without erasing adjacent coefficients. Designers typically pair this EEPROM with a microcontroller such as the 80C196KB or TMS320C25 for high-accuracy test instruments.
Recommandé
Point-of-Sale (POS) Terminal Transaction Logging
The AT28C010-12JC stores daily transaction batches, audit trails, and cryptographic keys in retail point-of-sale terminals where non-volatile retention is mandatory across power outages. Its 128-byte page-write capability efficiently handles batched transaction records, and the JEDEC-standard 32-PLCC footprint eases maintenance swap on legacy terminals. Designers typically implement a dual-bank scheme with a supervisory MCU and a lithium backup capacitor for ride-through, treating the AT28C010-12JC as the durable archive medium after super-capacitor discharge.
Recommandé
Avionics & Military Data Recorders
For MIL-STD-883 screened applications, the AT28C010 family supplies military temperature (-55C to +125C) variants used in flight data recorders, electronic flight instrument systems, and weapon-system controllers. The 1 Mbit density suits 4-8 hour mission-data buffering when paired with a microcontroller such as the 80C186 or Freescale MC68332. Designers should use the military 'JM883' suffix and confirm screening certificates at procurement time per MIL-PRF-38535 requirements.
Recommandé
Legacy Industrial Controller Firmware Replacement
When upgrading legacy 32-pin DIP-based 28C010 designs to surface-mount PLCC assemblies, the AT28C010-12JC enables a clean migration: existing firmware binaries are bit-for-bit compatible, and a low-profile 32-PLCC socket lets the part be field-replaced without hot-air rework. This pattern is common in CNC machine retrofits, textile machinery controllers, and elevator drive electronics where 20+ year field lifecycles require sustainable non-volatile memory supply chains.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour AT28C010-12JC — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | AT28C010-12JI | AT28C010E-12JC | AT28C010-15JC | AT28C010-10JC |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 32-PLCC (13.97 x 11.43 mm) | 32-PLCC - same | 32-PLCC - same | 32-PLCC - same | 32-PLCC - same |
| Memory Size | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) | 1 Mbit (128K x 8) |
| Access Time | 120 ns | 120 ns | 120 ns | 150 ns | 100 ns |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Operating Temperature | 0 C to +70 C (commercial) | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) |
| Page Write Time | 10 ms maximum | 10 ms | 10 ms | 10 ms | 10 ms |
| Active Power | 220 mW (max active) | 220 mW | Lower Iccsb (E-revision, datasheet addendum) | 220 mW | 220 mW |
Principaux différenciateurs
- Standard commercial temperature grade at lowest cost vs industrial/MIL siblings (vs AT28C010-12JI (industrial grade))
- Drop-in lower-power upgrade path via AT28C010E family (vs AT28C010E-12JC)
- 120 ns speed grade balances cost and 8-12 MHz bus compatibility (vs AT28C010-15JC (150 ns) and AT28C010-10JC (100 ns))
Notes de conception
Place a 0.1 uF ceramic decoupling capacitor within 5 mm of VCC (pin 32) and a bulk 10 uF tantalum or aluminum electrolytic within 25 mm of the package. According to the AT28C010 datasheet, current transients during page-write can reach 30 mA peak; insufficient decoupling can cause Vcc droop and write-disturbance of adjacent cells. Estimated: 0.35 mW typical standby and 220 mW active dissipation assume nominal Vcc = 5.0 V.
Route the OE and WE control signals with matched trace lengths (within 25 mm of each other) and keep them away from high-current switching traces. For 32-PLCC layouts, place a 32-pin PLCC socket (e.g. 3M Textool or Yamaichi) rather than soldering the chip directly to enable field replacement in long-lifecycle industrial products. Pin 1 is identified by a beveled edge or dot on the PLCC body - match it with the silk-screen orientation mark on the PCB.
Do not exceed 10 ms per page-write cycle - the device's internal timer terminates the write automatically but only if Vcc remains within 4.5-5.5 V. Brownouts or voltage spikes below 4.5 V during write can leave Data Protection latch in an undetermined state and corrupt adjacent bytes. Recommended: pair the AT28C010-12JC with a voltage supervisor (MAX1232 or equivalent) and gate CE with its RESET output.
The 5V TTL-compatible I/O bus can drive up to 4 mA per pin at 2.4 V Voh. For long bus connections (>100 mm backplane traces), add 33 ohm series damping resistors near the driver to suppress ringing on rising edges. Address and data lines should be length-matched within 10 mm to avoid bus skew during read cycles at 8 MHz+ frequencies. Comment-out the Data Protection latch if your firmware never issues WE to enable faster power-up reads.
Informations de conformité
RoHS and lead-free status marked unknown because the provided web snippets did not surface this information. The AT28C010 family is mature and Microchip has generally transitioned mature products to lead-free / RoHS-compliant versions; consult the manufacturer's material declaration or PCN database for definitive confirmation.
