EP20K200RC208-3 - APEX 20K 200K Gates FPGA, 208-RQFP | Intel
Référence : EP20K200RC208-3 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $145 | $145,00 |
| 10 | $132.5 | $1 325,00 |
| 100 | $118 | $11 800,00 |
| 500 | $105 | $52 500,00 |
| 1 000 | $95 | $95 000,00 |
EP20K200RC208-3 Présentation
What is an FPGA? A Field Programmable Gate Array is a reconfigurable semiconductor device that allows hardware logic to be programmed after manufacture. The APEX 20K family pioneered system-on-a-programmable-chip (SOPC) integration, embedding up to 1.6 Mbits of RAM directly into the fabric alongside logic and product-term resources, eliminating external SRAM in many designs. This architecture places the EP20K200RC208-3 in a hierarchy of: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit.
The MultiCore architecture combines three specialized structures: LUT-based logic for register-intensive functions, embedded array blocks (EABs) implementing memory or product-term logic, and a high-bandwidth interconnect network. The EP20K200RC208-3 supports up to 144 user I/O pins via LVDS signaling, with four phase-locked loops (PLLs) for clock management. The device supports hot-socketing, in-system programmability via IEEE 1149.1 JTAG, and operates across the industrial temperature range from -40°C to +85°C.
Typical applications include high-speed telecommunications interfaces, PCI bridge logic, DSP co-processing, and custom parallel bus controllers where the embedded memory eliminates the need for external SRAM. The 208-RQFP package provides a thermally enhanced footprint with an exposed pad for thermal dissipation, and the -3 speed grade places this part in the mid-range of APEX 20K performance options.
When designing with the EP20K200RC208-3, engineers should verify that the Quartus development toolchain (versions prior to 9.1) supports the device and that PCB thermal vias are placed under the exposed pad to maintain junction temperature under full I/O loading. Note that the APEX 20K family has reached end-of-life; consider Cyclone II or Cyclone III for new designs, and use this part only for maintenance of existing systems.
This page synthesizes distributor availability, parametric alternatives, and design considerations specific to the APEX 20K family that are not aggregated on any single manufacturer or distributor page, helping engineers evaluate lifecycle risk and replacement strategies.
Alternatives de remplacement direct pour EP20K200RC208-3 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP20K200RC208-3 (même facteur de forme et même empreinte) — différant par Process Technology, Family, Operating Temperature, Package, Speed Grade.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP20K200RC208-2
✅ Remplacement direct✓ En stock
$79.67 / unité
Voir la fiche technique →EP20K200RC208-1
✅ Remplacement direct✓ En stock
$78 / unité
Voir la fiche technique →EP20K200RC208-1N
✅ Remplacement direct✓ En stock
$18.1 / unité
Voir la fiche technique →EP20K200RC208-1X
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$35.8 / unité
Voir la fiche technique →EP20K200RC208-2X
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EP20K200RC208-3 Valeurs maximales et caractéristiques électriques
| Series | APEX 20K |
| Family | APEX-20K® |
| Logic Elements / Cells | 8,320 |
| Total System Gates | 200,000 |
| Embedded Memory (bits) | 106,496 |
| Number of I/O Pins | 144 |
| Boîtier | 208-RQFP Exposed Pad (BFQFP) |
| Type de montage | Surface Mount |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V |
| I/O Standard | LVDS (3.3 V / 2.5 V) |
| Maximum Operating Frequency | 167 MHz |
| PLLs | 4 |
| Speed Grade | -3 |
| Température de fonctionnement | -40°C to +85°C (Industrial) |
| Programming Interface | IEEE 1149.1 JTAG |
| In-System Programmable | Yes |
| Hot Socketing | Yes |
| Statut RoHS | Compliant |
Configuration des broches de EP20K200RC208-3
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | I/O — User I/O pin (bank 1) |
| Broche 5 | VCCINT — Core supply voltage 1.8 V |
| Broche 6 | I/O — User I/O pin (bank 1) |
| Broche 7 | I/O — User I/O pin (bank 1) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | GND — Ground |
| Broche 11 | I/O — User I/O pin (bank 1) |
| Broche 12 | I/O — User I/O pin (bank 1) |
| Broche 13 | I/O — User I/O pin (bank 1) |
| Broche 14 | I/O — User I/O pin (bank 1) |
| Broche 15 | I/O — User I/O pin (bank 1) |
| Broche 16 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 17 | I/O — User I/O pin (bank 2) |
| Broche 18 | I/O — User I/O pin (bank 2) |
| Broche 19 | I/O — User I/O pin (bank 2) |
| Broche 20 | I/O — User I/O pin (bank 2) |
| Broche 21 | I/O — User I/O pin (bank 2) |
| Broche 22 | GND — Ground |
| Broche 23 | I/O — User I/O pin (bank 2) |
| Broche 24 | I/O — User I/O pin (bank 2) |
| Broche 25 | I/O — User I/O pin (bank 2) |
| Broche 26 | I/O — User I/O pin (bank 2) |
| Broche 27 | I/O — User I/O pin (bank 2) |
| Broche 28 | VCCINT — Core supply voltage 1.8 V |
| Broche 29 | I/O — User I/O pin (bank 2) |
| Broche 30 | I/O — User I/O pin (bank 2) |
| Broche 31 | I/O — User I/O pin (bank 2) |
| Broche 32 | I/O — User I/O pin (bank 2) |
| Broche 33 | I/O — User I/O pin (bank 2) |
| Broche 34 | GND — Ground |
| Broche 35 | I/O — User I/O pin (bank 3) |
| Broche 36 | I/O — User I/O pin (bank 3) |
| Broche 37 | I/O — User I/O pin (bank 3) |
| Broche 38 | I/O — User I/O pin (bank 3) |
| Broche 39 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 40 | I/O — User I/O pin (bank 3) |
| Broche 41 | I/O — User I/O pin (bank 3) |
| Broche 42 | I/O — User I/O pin (bank 3) |
| Broche 43 | I/O — User I/O pin (bank 3) |
| Broche 44 | I/O — User I/O pin (bank 3) |
| Broche 45 | GND — Ground |
| Broche 46 | I/O — User I/O pin (bank 3) |
| Broche 47 | I/O — User I/O pin (bank 3) |
| Broche 48 | I/O — User I/O pin (bank 3) |
| Broche 49 | I/O — User I/O pin (bank 3) |
| Broche 50 | I/O — User I/O pin (bank 3) |
| Broche 51 | VCCINT — Core supply voltage 1.8 V |
| Broche 52 | I/O — User I/O pin (bank 4) |
| Broche 53 | I/O — User I/O pin (bank 4) |
| Broche 54 | I/O — User I/O pin (bank 4) |
| Broche 55 | I/O — User I/O pin (bank 4) |
| Broche 56 | I/O — User I/O pin (bank 4) |
| Broche 57 | GND — Ground |
| Broche 58 | I/O — User I/O pin (bank 4) |
| Broche 59 | I/O — User I/O pin (bank 4) |
| Broche 60 | I/O — User I/O pin (bank 4) |
| Broche 61 | I/O — User I/O pin (bank 4) |
| Broche 62 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 63 | I/O — User I/O pin (bank 4) |
| Broche 64 | I/O — User I/O pin (bank 4) |
| Broche 65 | I/O — User I/O pin (bank 4) |
| Broche 66 | I/O — User I/O pin (bank 4) |
| Broche 67 | I/O — User I/O pin (bank 4) |
| Broche 68 | GND — Ground |
| Broche 69 | I/O — User I/O pin (bank 5) |
| Broche 70 | I/O — User I/O pin (bank 5) |
| Broche 71 | I/O — User I/O pin (bank 5) |
| Broche 72 | I/O — User I/O pin (bank 5) |
| Broche 73 | I/O — User I/O pin (bank 5) |
| Broche 74 | VCCINT — Core supply voltage 1.8 V |
| Broche 75 | I/O — User I/O pin (bank 5) |
| Broche 76 | I/O — User I/O pin (bank 5) |
| Broche 77 | I/O — User I/O pin (bank 5) |
| Broche 78 | I/O — User I/O pin (bank 5) |
| Broche 79 | I/O — User I/O pin (bank 5) |
| Broche 80 | GND — Ground |
| Broche 81 | I/O — User I/O pin (bank 5) |
| Broche 82 | I/O — User I/O pin (bank 6) |
| Broche 83 | I/O — User I/O pin (bank 6) |
| Broche 84 | I/O — User I/O pin (bank 6) |
| Broche 85 | I/O — User I/O pin (bank 6) |
| Broche 86 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 87 | I/O — User I/O pin (bank 6) |
| Broche 88 | I/O — User I/O pin (bank 6) |
| Broche 89 | I/O — User I/O pin (bank 6) |
| Broche 90 | I/O — User I/O pin (bank 6) |
| Broche 91 | I/O — User I/O pin (bank 6) |
| Broche 92 | GND — Ground |
| Broche 93 | I/O — User I/O pin (bank 6) |
| Broche 94 | I/O — User I/O pin (bank 6) |
| Broche 95 | I/O — User I/O pin (bank 6) |
| Broche 96 | I/O — User I/O pin (bank 7) |
| Broche 97 | I/O — User I/O pin (bank 7) |
| Broche 98 | VCCINT — Core supply voltage 1.8 V |
| Broche 99 | I/O — User I/O pin (bank 7) |
| Broche 100 | I/O — User I/O pin (bank 7) |
| Broche 101 | I/O — User I/O pin (bank 7) |
| Broche 102 | I/O — User I/O pin (bank 7) |
| Broche 103 | I/O — User I/O pin (bank 7) |
| Broche 104 | GND — Ground |
| Broche 105 | I/O — User I/O pin (bank 7) |
| Broche 106 | I/O — User I/O pin (bank 7) |
| Broche 107 | I/O — User I/O pin (bank 7) |
| Broche 108 | I/O — User I/O pin (bank 8) |
| Broche 109 | I/O — User I/O pin (bank 8) |
| Broche 110 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 111 | I/O — User I/O pin (bank 8) |
| Broche 112 | I/O — User I/O pin (bank 8) |
| Broche 113 | I/O — User I/O pin (bank 8) |
| Broche 114 | I/O — User I/O pin (bank 8) |
| Broche 115 | I/O — User I/O pin (bank 8) |
| Broche 116 | GND — Ground |
| Broche 117 | I/O — User I/O pin (bank 8) |
| Broche 118 | I/O — User I/O pin (bank 8) |
| Broche 119 | I/O — User I/O pin (bank 8) |
| Broche 120 | I/O — User I/O pin (bank 8) |
| Broche 121 | I/O — User I/O pin (bank 8) |
| Broche 122 | VCCINT — Core supply voltage 1.8 V |
| Broche 123 | I/O — User I/O pin (bank 8) |
| Broche 124 | I/O — User I/O pin (bank 1) |
| Broche 125 | I/O — User I/O pin (bank 1) |
| Broche 126 | I/O — User I/O pin (bank 1) |
| Broche 127 | I/O — User I/O pin (bank 1) |
| Broche 128 | GND — Ground |
| Broche 129 | I/O — User I/O pin (bank 1) |
| Broche 130 | I/O — User I/O pin (bank 1) |
| Broche 131 | I/O — User I/O pin (bank 1) |
| Broche 132 | I/O — User I/O pin (bank 1) |
| Broche 133 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 134 | I/O — User I/O pin (bank 2) |
| Broche 135 | I/O — User I/O pin (bank 2) |
| Broche 136 | I/O — User I/O pin (bank 2) |
| Broche 137 | I/O — User I/O pin (bank 2) |
| Broche 138 | I/O — User I/O pin (bank 2) |
| Broche 139 | GND — Ground |
| Broche 140 | I/O — User I/O pin (bank 2) |
| Broche 141 | I/O — User I/O pin (bank 2) |
| Broche 142 | I/O — User I/O pin (bank 2) |
| Broche 143 | I/O — User I/O pin (bank 3) |
| Broche 144 | I/O — User I/O pin (bank 3) |
| Broche 145 | VCCINT — Core supply voltage 1.8 V |
| Broche 146 | I/O — User I/O pin (bank 3) |
| Broche 147 | I/O — User I/O pin (bank 3) |
| Broche 148 | I/O — User I/O pin (bank 3) |
| Broche 149 | I/O — User I/O pin (bank 3) |
| Broche 150 | I/O — User I/O pin (bank 3) |
| Broche 151 | GND — Ground |
| Broche 152 | I/O — User I/O pin (bank 3) |
| Broche 153 | I/O — User I/O pin (bank 3) |
| Broche 154 | I/O — User I/O pin (bank 3) |
| Broche 155 | I/O — User I/O pin (bank 4) |
| Broche 156 | I/O — User I/O pin (bank 4) |
| Broche 157 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 158 | I/O — User I/O pin (bank 4) |
| Broche 159 | I/O — User I/O pin (bank 4) |
| Broche 160 | I/O — User I/O pin (bank 4) |
| Broche 161 | I/O — User I/O pin (bank 4) |
| Broche 162 | I/O — User I/O pin (bank 4) |
| Broche 163 | GND — Ground |
| Broche 164 | I/O — User I/O pin (bank 4) |
| Broche 165 | I/O — User I/O pin (bank 4) |
| Broche 166 | I/O — User I/O pin (bank 4) |
| Broche 167 | I/O — User I/O pin (bank 5) |
| Broche 168 | I/O — User I/O pin (bank 5) |
| Broche 169 | VCCINT — Core supply voltage 1.8 V |
| Broche 170 | I/O — User I/O pin (bank 5) |
| Broche 171 | I/O — User I/O pin (bank 5) |
| Broche 172 | I/O — User I/O pin (bank 5) |
| Broche 173 | I/O — User I/O pin (bank 5) |
| Broche 174 | I/O — User I/O pin (bank 5) |
| Broche 175 | GND — Ground |
| Broche 176 | I/O — User I/O pin (bank 5) |
| Broche 177 | I/O — User I/O pin (bank 5) |
| Broche 178 | I/O — User I/O pin (bank 6) |
| Broche 179 | I/O — User I/O pin (bank 6) |
| Broche 180 | I/O — User I/O pin (bank 6) |
| Broche 181 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 182 | I/O — User I/O pin (bank 6) |
| Broche 183 | I/O — User I/O pin (bank 6) |
| Broche 184 | I/O — User I/O pin (bank 6) |
| Broche 185 | I/O — User I/O pin (bank 6) |
| Broche 186 | I/O — User I/O pin (bank 6) |
| Broche 187 | GND — Ground |
| Broche 188 | I/O — User I/O pin (bank 7) |
| Broche 189 | I/O — User I/O pin (bank 7) |
| Broche 190 | I/O — User I/O pin (bank 7) |
| Broche 191 | I/O — User I/O pin (bank 7) |
| Broche 192 | I/O — User I/O pin (bank 7) |
| Broche 193 | VCCINT — Core supply voltage 1.8 V |
| Broche 194 | I/O — User I/O pin (bank 7) |
| Broche 195 | I/O — User I/O pin (bank 7) |
| Broche 196 | I/O — User I/O pin (bank 7) |
| Broche 197 | I/O — User I/O pin (bank 8) |
| Broche 198 | I/O — User I/O pin (bank 8) |
| Broche 199 | GND — Ground |
| Broche 200 | I/O — User I/O pin (bank 8) |
| Broche 201 | I/O — User I/O pin (bank 8) |
| Broche 202 | I/O — User I/O pin (bank 8) |
| Broche 203 | I/O — User I/O pin (bank 8) |
| Broche 204 | I/O — User I/O pin (bank 8) |
| Broche 205 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Broche 206 | I/O — User I/O pin (bank 8) |
| Broche 207 | I/O — User I/O pin (bank 8) |
| Broche 208 | I/O — User I/O pin (bank 8) |
Applications typiques
EP20K200RC208-3 convient pour 6 applications: Telecommunications Interface Bridging, PCI Bus Bridge / Embedded Controller, DSP Co-Processor Front-End, Custom Parallel Bus Controller, Avionics Display / Radar Signal Pre-Processing, Test & Measurement Custom Logic.
Telecommunications Interface Bridging
The EP20K200RC208-3's 200K system gates and 106,496 bits of embedded memory make it well-suited for telecom line-card bridging functions where custom bus protocols must be translated between legacy TDM/E1 interfaces and modern packet backplanes. The MultiCore architecture's product-term logic handles small glue functions that would otherwise require a discrete CPLD, while LUT logic implements the main protocol state machines. The 167 MHz -3 speed grade supports high-speed serializer/deserializer bridging paths. The 208-RQFP with exposed pad allows hand-repairable assembly typical of telecom infrastructure boards.
Recommandé
PCI Bus Bridge / Embedded Controller
The EP20K200RC208-3 was widely deployed as a PCI 2.2 bridge controller in industrial single-board computers and custom embedded motherboards. Its 144 user I/O pins accommodate the full 32-bit/33 MHz PCI bus plus auxiliary GPIO, while the 8,320 logic elements implement target/master state machines, configuration space, and DMA engines. The 106 Kbits of embedded memory serve as scratch FIFOs for posted-write buffers. The -3 speed grade meets the 33 MHz PCI timing budget with margin, and the industrial temperature range suits factory automation deployments.
Recommandé
DSP Co-Processor Front-End
The APEX 20K's embedded array blocks (EABs) can implement RAM-based lookup tables, FIR filter coefficients, or sine/cosine tables, making the EP20K200RC208-3 suitable as a co-processor front-end for fixed-point DSP algorithms. The 106,496 bits of embedded memory map to 16 Kbits × 32 filter taps for dual-channel FIR filtering, and the 4 PLLs provide clock-domain crossing between the host DSP and the FPGA fabric. The 167 MHz fabric speed on the -3 grade sustains real-time sample rates up to 80 MSPS for moderate-complexity DSP pipelines.
Recommandé
Custom Parallel Bus Controller
Legacy industrial control systems often require custom parallel bus controllers for proprietary backplanes, SRAM/DRAM memory subsystems, or legacy peripheral chips. The EP20K200RC208-3 provides 144 user I/O pins sufficient for 32-bit data plus 24-bit address plus control signals, and the MultiCore architecture's product-term logic simplifies implementation of burst-mode handshakes and wait-state generation. The 208-RQFP package simplifies hand-prototyping and field replacement in existing industrial control cabinets.
Recommandé
Avionics Display / Radar Signal Pre-Processing
Legacy avionics systems and ground-based radar signal pre-processing units deployed the EP20K200RC208-3 for its radiation-tolerance characteristics and proven reliability profile. The 144 I/O pins accommodate parallel ADC interfaces at sample rates up to 80 MSPS, and the 106 Kbits of embedded memory implement moving-window integrators and CFAR detection. The -3 speed grade meets timing closure for multi-channel radar pre-processing at typical PRFs. Note that for new aerospace designs, rad-hard FPGAs from Microsemi or Xilinx are now preferred.
Recommandé
Test & Measurement Custom Logic
ATE (automatic test equipment) platforms and bench-top test instruments leverage the EP20K200RC208-3 to implement custom pattern generators, protocol decoders, and timing-edge placement logic. The 167 MHz fabric frequency on the -3 speed grade supports pattern generation at up to 80 MHz with sub-nanosecond resolution. The 8,320 logic elements implement complex state machines for boundary-scan, JTAG, and proprietary test protocols. The 208-RQFP package is friendly to iterative prototype revisions common in test equipment development.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP20K200RC208-3 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP20K200RC208-2 | EP20K200RC208-1 | EP20K200RC208-1N | EP20K200RC208-1X | EP20K200RC208-2X |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 208-RQFP Exposed Pad | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same |
| Speed Grade | -3 (167 MHz fmax) | -2 (~150 MHz) | -1 (~133 MHz) | -1 (~133 MHz) | -1 (~133 MHz) | -2 (~150 MHz) |
| Logic Elements | 8,320 | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) |
| Total System Gates | 200,000 | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) |
| Embedded Memory (bits) | 106,496 | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C (extended screen) | -40°C to +85°C (extended screen) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Highest speed grade in the 208-RQFP APEX 20K 200K family (vs EP20K200RC208-1)
- Pin-compatible upgrade path within the same package (vs EP20K200FC484-3)
- MultiCore architecture with product-term logic (vs Cyclone II EP2C20)
Notes de conception
The 208-RQFP package features an exposed thermal pad on the underside that MUST be soldered to a copper pour with thermal via stitching to the inner ground plane. Without proper thermal management, junction temperature can exceed 125°C under high I/O toggle activity, derating the industrial temperature range. Recommended: at least 9 thermal vias in a 3x3 grid under the pad, each 0.3 mm diameter, connected to a 1 oz copper inner plane.
The EP20K200RC208-3 requires separate VCCINT (1.8 V core) and VCCIO (3.3 V or 2.5 V I/O) rails with proper decoupling: 0.1 µF ceramic capacitors adjacent to every VCCINT/VCCIO pin pair, plus bulk 10–47 µF tantalum or polymer capacitors on each supply rail. Power sequencing should bring up VCCINT before VCCIO to avoid latchup; consult the APEX 20K datasheet family handbook for the recommended sequence.
Use Quartus 9.0 SP2 or earlier for synthesis, place-and-route, and bitstream generation. Newer Quartus versions do not support the APEX 20K family. Maintain a copy of the legacy MAX+PLUS II software for compatibility with older programming files. JTAG chain ordering must include all other 1149.1 devices on the board; use the Quartus Chain Description File (.cdf) format for programming file generation.
Do not assume new APEX 20K parts are still being manufactured — they have been obsolete since ~2005. All current supply is from remaining wafer stock at Rochester Electronics and authorized aftermarket distributors. Verify lot date codes and request pre-shipment electrical testing for any lot purchased on the open market, as old plastic-packaged parts may have moisture sensitivity issues (MSL) or solderability degradation.
Informations de conformité
RoHS compliance verified via Altera/Intel product documentation. APEX 20K family predates AEC-Q100 qualification programs; consult automotive applications handbook for any new automotive design.
