EP20K200RC208-3 - APEX 20K 200K Gates FPGA, 208-RQFP | Intel
N.º da peça: EP20K200RC208-3 ✗ Fim de vida| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $145 | $145,00 |
| 10 | $132.5 | $1.325,00 |
| 100 | $118 | $11.800,00 |
| 500 | $105 | $52.500,00 |
| 1.000 | $95 | $95.000,00 |
EP20K200RC208-3 Visão geral
What is an FPGA? A Field Programmable Gate Array is a reconfigurable semiconductor device that allows hardware logic to be programmed after manufacture. The APEX 20K family pioneered system-on-a-programmable-chip (SOPC) integration, embedding up to 1.6 Mbits of RAM directly into the fabric alongside logic and product-term resources, eliminating external SRAM in many designs. This architecture places the EP20K200RC208-3 in a hierarchy of: FPGA -> programmable logic device (PLD) -> logic IC -> integrated circuit.
The MultiCore architecture combines three specialized structures: LUT-based logic for register-intensive functions, embedded array blocks (EABs) implementing memory or product-term logic, and a high-bandwidth interconnect network. The EP20K200RC208-3 supports up to 144 user I/O pins via LVDS signaling, with four phase-locked loops (PLLs) for clock management. The device supports hot-socketing, in-system programmability via IEEE 1149.1 JTAG, and operates across the industrial temperature range from -40°C to +85°C.
Typical applications include high-speed telecommunications interfaces, PCI bridge logic, DSP co-processing, and custom parallel bus controllers where the embedded memory eliminates the need for external SRAM. The 208-RQFP package provides a thermally enhanced footprint with an exposed pad for thermal dissipation, and the -3 speed grade places this part in the mid-range of APEX 20K performance options.
When designing with the EP20K200RC208-3, engineers should verify that the Quartus development toolchain (versions prior to 9.1) supports the device and that PCB thermal vias are placed under the exposed pad to maintain junction temperature under full I/O loading. Note that the APEX 20K family has reached end-of-life; consider Cyclone II or Cyclone III for new designs, and use this part only for maintenance of existing systems.
This page synthesizes distributor availability, parametric alternatives, and design considerations specific to the APEX 20K family that are not aggregated on any single manufacturer or distributor page, helping engineers evaluate lifecycle risk and replacement strategies.
Alternativas drop-in para EP20K200RC208-3 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com EP20K200RC208-3 (mesmo formato e footprint) — diferindo em Process Technology, Family, Operating Temperature, Package, Speed Grade.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
EP20K200RC208-2
✅ Drop-In✓ Em estoque
$79.67 / unidade
Ver ficha técnica →EP20K200RC208-1
✅ Drop-In✓ Em estoque
$78 / unidade
Ver ficha técnica →EP20K200RC208-1N
✅ Drop-In✓ Em estoque
$18.1 / unidade
Ver ficha técnica →EP20K200RC208-1X
✅ Drop-In ⚠️ Especificações não verificadas✓ Em estoque
$35.8 / unidade
Ver ficha técnica →EP20K200RC208-2X
✅ Drop-In ⚠️ Especificações não verificadas📋 Alternativa de referência (fora do catálogo)
EP20K200RC208-3 Classificações máximas e características elétricas
| Series | APEX 20K |
| Family | APEX-20K® |
| Logic Elements / Cells | 8,320 |
| Total System Gates | 200,000 |
| Embedded Memory (bits) | 106,496 |
| Number of I/O Pins | 144 |
| Encapsulamento | 208-RQFP Exposed Pad (BFQFP) |
| Tipo de montagem | Surface Mount |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V |
| I/O Standard | LVDS (3.3 V / 2.5 V) |
| Maximum Operating Frequency | 167 MHz |
| PLLs | 4 |
| Speed Grade | -3 |
| Temperatura de operação | -40°C to +85°C (Industrial) |
| Programming Interface | IEEE 1149.1 JTAG |
| In-System Programmable | Yes |
| Hot Socketing | Yes |
| Status RoHS | Compliant |
Configuração de pinos do EP20K200RC208-3
| Pino 1 | I/O — User I/O pin (bank 1) |
| Pino 2 | I/O — User I/O pin (bank 1) |
| Pino 3 | I/O — User I/O pin (bank 1) |
| Pino 4 | I/O — User I/O pin (bank 1) |
| Pino 5 | VCCINT — Core supply voltage 1.8 V |
| Pino 6 | I/O — User I/O pin (bank 1) |
| Pino 7 | I/O — User I/O pin (bank 1) |
| Pino 8 | I/O — User I/O pin (bank 1) |
| Pino 9 | I/O — User I/O pin (bank 1) |
| Pino 10 | GND — Ground |
| Pino 11 | I/O — User I/O pin (bank 1) |
| Pino 12 | I/O — User I/O pin (bank 1) |
| Pino 13 | I/O — User I/O pin (bank 1) |
| Pino 14 | I/O — User I/O pin (bank 1) |
| Pino 15 | I/O — User I/O pin (bank 1) |
| Pino 16 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 17 | I/O — User I/O pin (bank 2) |
| Pino 18 | I/O — User I/O pin (bank 2) |
| Pino 19 | I/O — User I/O pin (bank 2) |
| Pino 20 | I/O — User I/O pin (bank 2) |
| Pino 21 | I/O — User I/O pin (bank 2) |
| Pino 22 | GND — Ground |
| Pino 23 | I/O — User I/O pin (bank 2) |
| Pino 24 | I/O — User I/O pin (bank 2) |
| Pino 25 | I/O — User I/O pin (bank 2) |
| Pino 26 | I/O — User I/O pin (bank 2) |
| Pino 27 | I/O — User I/O pin (bank 2) |
| Pino 28 | VCCINT — Core supply voltage 1.8 V |
| Pino 29 | I/O — User I/O pin (bank 2) |
| Pino 30 | I/O — User I/O pin (bank 2) |
| Pino 31 | I/O — User I/O pin (bank 2) |
| Pino 32 | I/O — User I/O pin (bank 2) |
| Pino 33 | I/O — User I/O pin (bank 2) |
| Pino 34 | GND — Ground |
| Pino 35 | I/O — User I/O pin (bank 3) |
| Pino 36 | I/O — User I/O pin (bank 3) |
| Pino 37 | I/O — User I/O pin (bank 3) |
| Pino 38 | I/O — User I/O pin (bank 3) |
| Pino 39 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 40 | I/O — User I/O pin (bank 3) |
| Pino 41 | I/O — User I/O pin (bank 3) |
| Pino 42 | I/O — User I/O pin (bank 3) |
| Pino 43 | I/O — User I/O pin (bank 3) |
| Pino 44 | I/O — User I/O pin (bank 3) |
| Pino 45 | GND — Ground |
| Pino 46 | I/O — User I/O pin (bank 3) |
| Pino 47 | I/O — User I/O pin (bank 3) |
| Pino 48 | I/O — User I/O pin (bank 3) |
| Pino 49 | I/O — User I/O pin (bank 3) |
| Pino 50 | I/O — User I/O pin (bank 3) |
| Pino 51 | VCCINT — Core supply voltage 1.8 V |
| Pino 52 | I/O — User I/O pin (bank 4) |
| Pino 53 | I/O — User I/O pin (bank 4) |
| Pino 54 | I/O — User I/O pin (bank 4) |
| Pino 55 | I/O — User I/O pin (bank 4) |
| Pino 56 | I/O — User I/O pin (bank 4) |
| Pino 57 | GND — Ground |
| Pino 58 | I/O — User I/O pin (bank 4) |
| Pino 59 | I/O — User I/O pin (bank 4) |
| Pino 60 | I/O — User I/O pin (bank 4) |
| Pino 61 | I/O — User I/O pin (bank 4) |
| Pino 62 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 63 | I/O — User I/O pin (bank 4) |
| Pino 64 | I/O — User I/O pin (bank 4) |
| Pino 65 | I/O — User I/O pin (bank 4) |
| Pino 66 | I/O — User I/O pin (bank 4) |
| Pino 67 | I/O — User I/O pin (bank 4) |
| Pino 68 | GND — Ground |
| Pino 69 | I/O — User I/O pin (bank 5) |
| Pino 70 | I/O — User I/O pin (bank 5) |
| Pino 71 | I/O — User I/O pin (bank 5) |
| Pino 72 | I/O — User I/O pin (bank 5) |
| Pino 73 | I/O — User I/O pin (bank 5) |
| Pino 74 | VCCINT — Core supply voltage 1.8 V |
| Pino 75 | I/O — User I/O pin (bank 5) |
| Pino 76 | I/O — User I/O pin (bank 5) |
| Pino 77 | I/O — User I/O pin (bank 5) |
| Pino 78 | I/O — User I/O pin (bank 5) |
| Pino 79 | I/O — User I/O pin (bank 5) |
| Pino 80 | GND — Ground |
| Pino 81 | I/O — User I/O pin (bank 5) |
| Pino 82 | I/O — User I/O pin (bank 6) |
| Pino 83 | I/O — User I/O pin (bank 6) |
| Pino 84 | I/O — User I/O pin (bank 6) |
| Pino 85 | I/O — User I/O pin (bank 6) |
| Pino 86 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 87 | I/O — User I/O pin (bank 6) |
| Pino 88 | I/O — User I/O pin (bank 6) |
| Pino 89 | I/O — User I/O pin (bank 6) |
| Pino 90 | I/O — User I/O pin (bank 6) |
| Pino 91 | I/O — User I/O pin (bank 6) |
| Pino 92 | GND — Ground |
| Pino 93 | I/O — User I/O pin (bank 6) |
| Pino 94 | I/O — User I/O pin (bank 6) |
| Pino 95 | I/O — User I/O pin (bank 6) |
| Pino 96 | I/O — User I/O pin (bank 7) |
| Pino 97 | I/O — User I/O pin (bank 7) |
| Pino 98 | VCCINT — Core supply voltage 1.8 V |
| Pino 99 | I/O — User I/O pin (bank 7) |
| Pino 100 | I/O — User I/O pin (bank 7) |
| Pino 101 | I/O — User I/O pin (bank 7) |
| Pino 102 | I/O — User I/O pin (bank 7) |
| Pino 103 | I/O — User I/O pin (bank 7) |
| Pino 104 | GND — Ground |
| Pino 105 | I/O — User I/O pin (bank 7) |
| Pino 106 | I/O — User I/O pin (bank 7) |
| Pino 107 | I/O — User I/O pin (bank 7) |
| Pino 108 | I/O — User I/O pin (bank 8) |
| Pino 109 | I/O — User I/O pin (bank 8) |
| Pino 110 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 111 | I/O — User I/O pin (bank 8) |
| Pino 112 | I/O — User I/O pin (bank 8) |
| Pino 113 | I/O — User I/O pin (bank 8) |
| Pino 114 | I/O — User I/O pin (bank 8) |
| Pino 115 | I/O — User I/O pin (bank 8) |
| Pino 116 | GND — Ground |
| Pino 117 | I/O — User I/O pin (bank 8) |
| Pino 118 | I/O — User I/O pin (bank 8) |
| Pino 119 | I/O — User I/O pin (bank 8) |
| Pino 120 | I/O — User I/O pin (bank 8) |
| Pino 121 | I/O — User I/O pin (bank 8) |
| Pino 122 | VCCINT — Core supply voltage 1.8 V |
| Pino 123 | I/O — User I/O pin (bank 8) |
| Pino 124 | I/O — User I/O pin (bank 1) |
| Pino 125 | I/O — User I/O pin (bank 1) |
| Pino 126 | I/O — User I/O pin (bank 1) |
| Pino 127 | I/O — User I/O pin (bank 1) |
| Pino 128 | GND — Ground |
| Pino 129 | I/O — User I/O pin (bank 1) |
| Pino 130 | I/O — User I/O pin (bank 1) |
| Pino 131 | I/O — User I/O pin (bank 1) |
| Pino 132 | I/O — User I/O pin (bank 1) |
| Pino 133 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 134 | I/O — User I/O pin (bank 2) |
| Pino 135 | I/O — User I/O pin (bank 2) |
| Pino 136 | I/O — User I/O pin (bank 2) |
| Pino 137 | I/O — User I/O pin (bank 2) |
| Pino 138 | I/O — User I/O pin (bank 2) |
| Pino 139 | GND — Ground |
| Pino 140 | I/O — User I/O pin (bank 2) |
| Pino 141 | I/O — User I/O pin (bank 2) |
| Pino 142 | I/O — User I/O pin (bank 2) |
| Pino 143 | I/O — User I/O pin (bank 3) |
| Pino 144 | I/O — User I/O pin (bank 3) |
| Pino 145 | VCCINT — Core supply voltage 1.8 V |
| Pino 146 | I/O — User I/O pin (bank 3) |
| Pino 147 | I/O — User I/O pin (bank 3) |
| Pino 148 | I/O — User I/O pin (bank 3) |
| Pino 149 | I/O — User I/O pin (bank 3) |
| Pino 150 | I/O — User I/O pin (bank 3) |
| Pino 151 | GND — Ground |
| Pino 152 | I/O — User I/O pin (bank 3) |
| Pino 153 | I/O — User I/O pin (bank 3) |
| Pino 154 | I/O — User I/O pin (bank 3) |
| Pino 155 | I/O — User I/O pin (bank 4) |
| Pino 156 | I/O — User I/O pin (bank 4) |
| Pino 157 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 158 | I/O — User I/O pin (bank 4) |
| Pino 159 | I/O — User I/O pin (bank 4) |
| Pino 160 | I/O — User I/O pin (bank 4) |
| Pino 161 | I/O — User I/O pin (bank 4) |
| Pino 162 | I/O — User I/O pin (bank 4) |
| Pino 163 | GND — Ground |
| Pino 164 | I/O — User I/O pin (bank 4) |
| Pino 165 | I/O — User I/O pin (bank 4) |
| Pino 166 | I/O — User I/O pin (bank 4) |
| Pino 167 | I/O — User I/O pin (bank 5) |
| Pino 168 | I/O — User I/O pin (bank 5) |
| Pino 169 | VCCINT — Core supply voltage 1.8 V |
| Pino 170 | I/O — User I/O pin (bank 5) |
| Pino 171 | I/O — User I/O pin (bank 5) |
| Pino 172 | I/O — User I/O pin (bank 5) |
| Pino 173 | I/O — User I/O pin (bank 5) |
| Pino 174 | I/O — User I/O pin (bank 5) |
| Pino 175 | GND — Ground |
| Pino 176 | I/O — User I/O pin (bank 5) |
| Pino 177 | I/O — User I/O pin (bank 5) |
| Pino 178 | I/O — User I/O pin (bank 6) |
| Pino 179 | I/O — User I/O pin (bank 6) |
| Pino 180 | I/O — User I/O pin (bank 6) |
| Pino 181 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 182 | I/O — User I/O pin (bank 6) |
| Pino 183 | I/O — User I/O pin (bank 6) |
| Pino 184 | I/O — User I/O pin (bank 6) |
| Pino 185 | I/O — User I/O pin (bank 6) |
| Pino 186 | I/O — User I/O pin (bank 6) |
| Pino 187 | GND — Ground |
| Pino 188 | I/O — User I/O pin (bank 7) |
| Pino 189 | I/O — User I/O pin (bank 7) |
| Pino 190 | I/O — User I/O pin (bank 7) |
| Pino 191 | I/O — User I/O pin (bank 7) |
| Pino 192 | I/O — User I/O pin (bank 7) |
| Pino 193 | VCCINT — Core supply voltage 1.8 V |
| Pino 194 | I/O — User I/O pin (bank 7) |
| Pino 195 | I/O — User I/O pin (bank 7) |
| Pino 196 | I/O — User I/O pin (bank 7) |
| Pino 197 | I/O — User I/O pin (bank 8) |
| Pino 198 | I/O — User I/O pin (bank 8) |
| Pino 199 | GND — Ground |
| Pino 200 | I/O — User I/O pin (bank 8) |
| Pino 201 | I/O — User I/O pin (bank 8) |
| Pino 202 | I/O — User I/O pin (bank 8) |
| Pino 203 | I/O — User I/O pin (bank 8) |
| Pino 204 | I/O — User I/O pin (bank 8) |
| Pino 205 | VCCIO — I/O supply voltage 3.3 V / 2.5 V |
| Pino 206 | I/O — User I/O pin (bank 8) |
| Pino 207 | I/O — User I/O pin (bank 8) |
| Pino 208 | I/O — User I/O pin (bank 8) |
Aplicações típicas
EP20K200RC208-3 é adequado para 6 aplicaçãos: Telecommunications Interface Bridging, PCI Bus Bridge / Embedded Controller, DSP Co-Processor Front-End, Custom Parallel Bus Controller, Avionics Display / Radar Signal Pre-Processing, Test & Measurement Custom Logic.
Telecommunications Interface Bridging
The EP20K200RC208-3's 200K system gates and 106,496 bits of embedded memory make it well-suited for telecom line-card bridging functions where custom bus protocols must be translated between legacy TDM/E1 interfaces and modern packet backplanes. The MultiCore architecture's product-term logic handles small glue functions that would otherwise require a discrete CPLD, while LUT logic implements the main protocol state machines. The 167 MHz -3 speed grade supports high-speed serializer/deserializer bridging paths. The 208-RQFP with exposed pad allows hand-repairable assembly typical of telecom infrastructure boards.
Recomendado
PCI Bus Bridge / Embedded Controller
The EP20K200RC208-3 was widely deployed as a PCI 2.2 bridge controller in industrial single-board computers and custom embedded motherboards. Its 144 user I/O pins accommodate the full 32-bit/33 MHz PCI bus plus auxiliary GPIO, while the 8,320 logic elements implement target/master state machines, configuration space, and DMA engines. The 106 Kbits of embedded memory serve as scratch FIFOs for posted-write buffers. The -3 speed grade meets the 33 MHz PCI timing budget with margin, and the industrial temperature range suits factory automation deployments.
Recomendado
DSP Co-Processor Front-End
The APEX 20K's embedded array blocks (EABs) can implement RAM-based lookup tables, FIR filter coefficients, or sine/cosine tables, making the EP20K200RC208-3 suitable as a co-processor front-end for fixed-point DSP algorithms. The 106,496 bits of embedded memory map to 16 Kbits × 32 filter taps for dual-channel FIR filtering, and the 4 PLLs provide clock-domain crossing between the host DSP and the FPGA fabric. The 167 MHz fabric speed on the -3 grade sustains real-time sample rates up to 80 MSPS for moderate-complexity DSP pipelines.
Recomendado
Custom Parallel Bus Controller
Legacy industrial control systems often require custom parallel bus controllers for proprietary backplanes, SRAM/DRAM memory subsystems, or legacy peripheral chips. The EP20K200RC208-3 provides 144 user I/O pins sufficient for 32-bit data plus 24-bit address plus control signals, and the MultiCore architecture's product-term logic simplifies implementation of burst-mode handshakes and wait-state generation. The 208-RQFP package simplifies hand-prototyping and field replacement in existing industrial control cabinets.
Recomendado
Avionics Display / Radar Signal Pre-Processing
Legacy avionics systems and ground-based radar signal pre-processing units deployed the EP20K200RC208-3 for its radiation-tolerance characteristics and proven reliability profile. The 144 I/O pins accommodate parallel ADC interfaces at sample rates up to 80 MSPS, and the 106 Kbits of embedded memory implement moving-window integrators and CFAR detection. The -3 speed grade meets timing closure for multi-channel radar pre-processing at typical PRFs. Note that for new aerospace designs, rad-hard FPGAs from Microsemi or Xilinx are now preferred.
Recomendado
Test & Measurement Custom Logic
ATE (automatic test equipment) platforms and bench-top test instruments leverage the EP20K200RC208-3 to implement custom pattern generators, protocol decoders, and timing-edge placement logic. The 167 MHz fabric frequency on the -3 speed grade supports pattern generation at up to 80 MHz with sub-nanosecond resolution. The 8,320 logic elements implement complex state machines for boundary-scan, JTAG, and proprietary test protocols. The 208-RQFP package is friendly to iterative prototype revisions common in test equipment development.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para EP20K200RC208-3 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | EP20K200RC208-2 | EP20K200RC208-1 | EP20K200RC208-1N | EP20K200RC208-1X | EP20K200RC208-2X |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 208-RQFP Exposed Pad | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same | 208-RQFP Exposed Pad - same |
| Speed Grade | -3 (167 MHz fmax) | -2 (~150 MHz) | -1 (~133 MHz) | -1 (~133 MHz) | -1 (~133 MHz) | -2 (~150 MHz) |
| Logic Elements | 8,320 | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) | 8,320 (same die) |
| Total System Gates | 200,000 | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) | 200,000 (same die) |
| Embedded Memory (bits) | 106,496 | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) | 106,496 (same die) |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C | -40°C to +85°C (extended screen) | -40°C to +85°C (extended screen) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principais diferenciais
- Highest speed grade in the 208-RQFP APEX 20K 200K family (vs EP20K200RC208-1)
- Pin-compatible upgrade path within the same package (vs EP20K200FC484-3)
- MultiCore architecture with product-term logic (vs Cyclone II EP2C20)
Notas de projeto
The 208-RQFP package features an exposed thermal pad on the underside that MUST be soldered to a copper pour with thermal via stitching to the inner ground plane. Without proper thermal management, junction temperature can exceed 125°C under high I/O toggle activity, derating the industrial temperature range. Recommended: at least 9 thermal vias in a 3x3 grid under the pad, each 0.3 mm diameter, connected to a 1 oz copper inner plane.
The EP20K200RC208-3 requires separate VCCINT (1.8 V core) and VCCIO (3.3 V or 2.5 V I/O) rails with proper decoupling: 0.1 µF ceramic capacitors adjacent to every VCCINT/VCCIO pin pair, plus bulk 10–47 µF tantalum or polymer capacitors on each supply rail. Power sequencing should bring up VCCINT before VCCIO to avoid latchup; consult the APEX 20K datasheet family handbook for the recommended sequence.
Use Quartus 9.0 SP2 or earlier for synthesis, place-and-route, and bitstream generation. Newer Quartus versions do not support the APEX 20K family. Maintain a copy of the legacy MAX+PLUS II software for compatibility with older programming files. JTAG chain ordering must include all other 1149.1 devices on the board; use the Quartus Chain Description File (.cdf) format for programming file generation.
Do not assume new APEX 20K parts are still being manufactured — they have been obsolete since ~2005. All current supply is from remaining wafer stock at Rochester Electronics and authorized aftermarket distributors. Verify lot date codes and request pre-shipment electrical testing for any lot purchased on the open market, as old plastic-packaged parts may have moisture sensitivity issues (MSL) or solderability degradation.
Informações de conformidade
RoHS compliance verified via Altera/Intel product documentation. APEX 20K family predates AEC-Q100 qualification programs; consult automotive applications handbook for any new automotive design.
