EP20K60ETC144-3N - APEX-20KE FPGA 60K Gates 2560 Logic Elements 144-LQFP | Intel
Référence : EP20K60ETC144-3N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $145 | $145,00 |
| 10 | $132.5 | $1 325,00 |
| 100 | $118 | $11 800,00 |
| 500 | $105 | $52 500,00 |
| 1 000 | $92 | $92 000,00 |
EP20K60ETC144-3N Présentation
A field-programmable gate array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that the designer programs after manufacture to implement arbitrary digital functions. APEX-20KE specifically introduced MultiCore™ architecture integrating look-up tables, product-term logic, and embedded system-on-a-programmable-chip (SOPC) blocks, which placed it within the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based FPGA → APEX-20KE. This hierarchy matters when designers compare it against later Cyclone, Stratix or competing Xilinx Spartan families.
Key features include 32,768 bits of embedded SRAM (ESB), 92 maximum user I/O, in-system programmability via IEEE 1149.1 JTAG, dedicated PLL-style clock networks (LVDSL/LVDS-style high-speed inputs available on selected banks), and a low-power 1.8V core. The device is offered in the commercial 0 °C to +85 °C temperature grade and uses a gull-wing surface-mount 144-LQFP (LFQFP code) with square body for standard SMT reflow.
Architecturally, the APEX-20KE family combines fast on-chip SRAM and product-term logic with high-speed interconnect, enabling designers to consolidate multiple CPLDs and discrete glue logic into a single device. The 2560 logic cells and 60K typical gate count put this part in the lower-mid-density tier of legacy Intel/Altera programmable logic, often used for bus bridges, custom peripherals, and pre-processing pipelines feeding a host processor.
Typical applications include telecom line-card interface logic, industrial control and instrumentation front ends, video pixel processing, military/aerospace retrofit boards where long-term Altera tooling is preserved, and legacy ASIC-replacement designs. The 144-LQFP footprint allows hand-rework and prototyping that smaller BGA packages cannot.
When designing with this FPGA, ensure the Quartus II (or MAX+PLUS II) toolchain version supports the APEX-20KE device family - newer Quartus releases have removed legacy device support. Plan power-rail decoupling for the 1.8V VCCINT and any 2.5V/3.3V VCCIO bank supplies per the APEX-20KE handbook.
This page synthesizes distributor inventory, pin-compatible APEX-20KE drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour EP20K60ETC144-3N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP20K60ETC144-3N (même facteur de forme et même empreinte) — différant par Operating Temperature, Package, Speed Grade, Family, Core Supply Voltage (VCCINT).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP20K60ETC144-3
✅ Remplacement direct✓ En stock
$26.8 / unité
Voir la fiche technique →EP20K60ETC144-2N
✅ Remplacement direct✓ En stock
$65 / unité
Voir la fiche technique →EP20K60ETC144-2X
✅ Remplacement direct✓ En stock
$51.8 / unité
Voir la fiche technique →EP20K60ETC144-1X
✅ Remplacement direct✓ En stock
$152 / unité
Voir la fiche technique →EP20K60EFI144-2X
✅ Remplacement direct✓ En stock
$65 / unité
Voir la fiche technique →EP20K60EFC144-2XN
✅ Remplacement direct✓ En stock
$152 / unité
Voir la fiche technique →EP20K60ETC144-3N Valeurs maximales et caractéristiques électriques
| Family | APEX-20KE |
| Typical Gate Count | 60,000 gates |
| Logic Elements / Cells | 2,560 |
| Embedded Memory (ESB) | 32,768 bits |
| Maximum User I/O | 92 |
| Core Supply Voltage (VCCINT) | 1.8 V |
| Internal Frequency | 160 MHz to 182 MHz |
| Propagation Delay | 1.72 ns |
| Process Technology | 0.22 µm CMOS |
| Operating Temperature (Commercial) | 0 °C to +85 °C |
| Boîtier | 144-LQFP (LFQFP, gull-wing, square body) |
| Type de montage | Surface Mount |
| Logic Family | CMOS |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) |
| Statut RoHS | unknown |
Configuration des broches de EP20K60ETC144-3N
| Broche 1 | I/O — User I/O bank 1 |
| Broche 2 | I/O — User I/O bank 1 |
| Broche 3 | VCCIO1 — I/O bank 1 supply (2.5V or 3.3V) |
| Broche 4 | I/O — User I/O bank 1 |
| Broche 5 | I/O — User I/O bank 1 |
| Broche 6 | I/O — User I/O bank 1 |
| Broche 7 | GND — Ground |
| Broche 8 | I/O — User I/O bank 1 |
| Broche 9 | I/O — User I/O bank 1 |
| Broche 10 | I/O — User I/O bank 1 |
| Broche 11 | I/O — User I/O bank 1 |
| Broche 12 | VCCIO1 — I/O bank 1 supply |
| Broche 13 | I/O — User I/O bank 1 |
| Broche 14 | I/O — User I/O bank 1 |
| Broche 15 | I/O — User I/O bank 1 |
| Broche 16 | I/O — User I/O bank 1 |
| Broche 17 | GND — Ground |
| Broche 18 | I/O — User I/O bank 1 |
| Broche 19 | I/O — User I/O bank 1 |
| Broche 20 | I/O — User I/O bank 1 |
| Broche 21 | VCCINT — Core supply 1.8V |
| Broche 22 | I/O — User I/O bank 2 |
| Broche 23 | I/O — User I/O bank 2 |
| Broche 24 | I/O — User I/O bank 2 |
| Broche 25 | I/O — User I/O bank 2 |
| Broche 26 | I/O — User I/O bank 2 |
| Broche 27 | GND — Ground |
| Broche 28 | I/O — User I/O bank 2 |
| Broche 29 | I/O — User I/O bank 2 |
| Broche 30 | CLK0 — Dedicated clock input 0 |
| Broche 31 | CLK1 — Dedicated clock input 1 |
| Broche 32 | I/O — User I/O bank 2 |
| Broche 33 | I/O — User I/O bank 2 |
| Broche 34 | I/O — User I/O bank 2 |
| Broche 35 | VCCIO2 — I/O bank 2 supply |
| Broche 36 | I/O — User I/O bank 2 |
| Broche 37 | I/O — User I/O bank 2 |
| Broche 38 | I/O — User I/O bank 2 |
| Broche 39 | GND — Ground |
| Broche 40 | I/O — User I/O bank 2 |
| Broche 41 | I/O — User I/O bank 2 |
| Broche 42 | I/O — User I/O bank 2 |
| Broche 43 | I/O — User I/O bank 2 |
| Broche 44 | I/O — User I/O bank 2 |
| Broche 45 | VCCIO2 — I/O bank 2 supply |
| Broche 46 | I/O — User I/O bank 2 |
| Broche 47 | I/O — User I/O bank 2 |
| Broche 48 | I/O — User I/O bank 2 |
| Broche 49 | I/O — User I/O bank 2 |
| Broche 50 | GND — Ground |
| Broche 51 | I/O — User I/O bank 2 |
| Broche 52 | I/O — User I/O bank 2 |
| Broche 53 | I/O — User I/O bank 2 |
| Broche 54 | I/O — User I/O bank 2 |
| Broche 55 | VCCINT — Core supply 1.8V |
| Broche 56 | I/O — User I/O bank 3 |
| Broche 57 | I/O — User I/O bank 3 |
| Broche 58 | I/O — User I/O bank 3 |
| Broche 59 | I/O — User I/O bank 3 |
| Broche 60 | I/O — User I/O bank 3 |
| Broche 61 | GND — Ground |
| Broche 62 | I/O — User I/O bank 3 |
| Broche 63 | I/O — User I/O bank 3 |
| Broche 64 | CLK2 — Dedicated clock input 2 |
| Broche 65 | CLK3 — Dedicated clock input 3 |
| Broche 66 | I/O — User I/O bank 3 |
| Broche 67 | I/O — User I/O bank 3 |
| Broche 68 | I/O — User I/O bank 3 |
| Broche 69 | VCCIO3 — I/O bank 3 supply |
| Broche 70 | I/O — User I/O bank 3 |
| Broche 71 | I/O — User I/O bank 3 |
| Broche 72 | I/O — User I/O bank 3 |
| Broche 73 | GND — Ground |
| Broche 74 | I/O — User I/O bank 3 |
| Broche 75 | I/O — User I/O bank 3 |
| Broche 76 | I/O — User I/O bank 3 |
| Broche 77 | I/O — User I/O bank 3 |
| Broche 78 | I/O — User I/O bank 3 |
| Broche 79 | VCCIO3 — I/O bank 3 supply |
| Broche 80 | I/O — User I/O bank 3 |
| Broche 81 | I/O — User I/O bank 3 |
| Broche 82 | I/O — User I/O bank 3 |
| Broche 83 | I/O — User I/O bank 3 |
| Broche 84 | GND — Ground |
| Broche 85 | I/O — User I/O bank 3 |
| Broche 86 | I/O — User I/O bank 3 |
| Broche 87 | I/O — User I/O bank 3 |
| Broche 88 | I/O — User I/O bank 3 |
| Broche 89 | VCCINT — Core supply 1.8V |
| Broche 90 | I/O — User I/O bank 4 |
| Broche 91 | I/O — User I/O bank 4 |
| Broche 92 | I/O — User I/O bank 4 |
| Broche 93 | I/O — User I/O bank 4 |
| Broche 94 | I/O — User I/O bank 4 |
| Broche 95 | GND — Ground |
| Broche 96 | I/O — User I/O bank 4 |
| Broche 97 | I/O — User I/O bank 4 |
| Broche 98 | TDI — JTAG test data in |
| Broche 99 | TMS — JTAG test mode select |
| Broche 100 | TCK — JTAG test clock |
| Broche 101 | TDO — JTAG test data out |
| Broche 102 | I/O — User I/O bank 4 |
| Broche 103 | I/O — User I/O bank 4 |
| Broche 104 | I/O — User I/O bank 4 |
| Broche 105 | VCCIO4 — I/O bank 4 supply |
| Broche 106 | I/O — User I/O bank 4 |
| Broche 107 | I/O — User I/O bank 4 |
| Broche 108 | I/O — User I/O bank 4 |
| Broche 109 | GND — Ground |
| Broche 110 | I/O — User I/O bank 4 |
| Broche 111 | I/O — User I/O bank 4 |
| Broche 112 | MSEL0 — Configuration mode select 0 |
| Broche 113 | MSEL1 — Configuration mode select 1 |
| Broche 114 | nCONFIG — Configuration begin (active low) |
| Broche 115 | nSTATUS — Configuration status (active low) |
| Broche 116 | I/O — User I/O bank 4 |
| Broche 117 | I/O — User I/O bank 4 |
| Broche 118 | VCCIO4 — I/O bank 4 supply |
| Broche 119 | I/O — User I/O bank 4 |
| Broche 120 | I/O — User I/O bank 4 |
| Broche 121 | I/O — User I/O bank 4 |
| Broche 122 | GND — Ground |
| Broche 123 | I/O — User I/O bank 4 |
| Broche 124 | I/O — User I/O bank 4 |
| Broche 125 | I/O — User I/O bank 1 |
| Broche 126 | I/O — User I/O bank 1 |
| Broche 127 | I/O — User I/O bank 1 |
| Broche 128 | I/O — User I/O bank 1 |
| Broche 129 | VCCINT — Core supply 1.8V |
| Broche 130 | I/O — User I/O bank 1 |
| Broche 131 | I/O — User I/O bank 1 |
| Broche 132 | I/O — User I/O bank 1 |
| Broche 133 | I/O — User I/O bank 1 |
| Broche 134 | I/O — User I/O bank 1 |
| Broche 135 | GND — Ground |
| Broche 136 | I/O — User I/O bank 1 |
| Broche 137 | I/O — User I/O bank 1 |
| Broche 138 | I/O — User I/O bank 1 |
| Broche 139 | I/O — User I/O bank 1 |
| Broche 140 | I/O — User I/O bank 1 |
| Broche 141 | VCCIO1 — I/O bank 1 supply |
| Broche 142 | I/O — User I/O bank 1 |
| Broche 143 | I/O — User I/O bank 1 |
| Broche 144 | I/O — User I/O bank 1 |
Applications typiques
EP20K60ETC144-3N convient pour 6 applications: Telecom Line-Card Interface Logic, Industrial Control & Instrumentation Front Ends, Video Pixel Processing & Display Pipelines, Legacy ASIC Replacement & Bus Bridging, Military & Aerospace Retrofit Boards, DSP Front-End Pre-Processing.
Telecom Line-Card Interface Logic
The EP20K60ETC144-3N is well suited to telecom line-card glue-logic because its 60K gates, 2,560 logic elements, and 92 user I/Os provide enough density to bridge an upstream framer to backplane serializer/deserializer devices. The 1.8V core plus 2.5V/3.3V VCCIO bank flexibility supports LVTTL and LVCMOS I/O standards commonly required on T1/E1 and SONET/SDH interface cards. Placed between the PHY and the network processor, it implements framing, alarm extraction, and per-channel HDLC encapsulation without consuming the host CPU. Compared with discrete 74-series logic it consolidates the BOM, and the 144-LQFP package enables hand rework on legacy line-card spares.
Recommandé
Industrial Control & Instrumentation Front Ends
The EP20K60ETC144-3N fits industrial front-end designs thanks to its 60K gates, 32,768 bits of embedded SRAM for sample buffering, and 92 user I/Os that can fan out to multiple sensor conditioning channels. The 1.72 ns propagation delay supports real-time encoder quadrature decoding and PWM generation for motor-control loops. Implemented on a PLC analog-input card, the FPGA timestamps samples and pre-processes them before handing them to the MCU; the commercial 0 °C to +85 °C operating range covers most indoor control cabinets. The 144-LQFP gull-wing package withstands hand-soldering for prototype iterations.
Recommandé
Video Pixel Processing & Display Pipelines
The EP20K60ETC144-3N enables mid-resolution video pixel pipelines because its 182 MHz internal frequency can clock a single channel of SD/HD pixel data with sufficient margin for color-space conversion and overlay composition. The 92 user I/Os accommodate parallel RGB or LVDS display interfaces plus side-band control signals (HSYNC, VSYNC, DE, backlight PWM). Deployed between a video decoder ASIC and an LCD driver, the FPGA performs scaling, gamma correction, and on-screen display blending without requiring an external frame buffer in simple cases. The 144-LQFP footprint eases retrofitting into existing 4-layer video boards.
Recommandé
Legacy ASIC Replacement & Bus Bridging
The EP20K60ETC144-3N is an excellent ASIC replacement target because the APEX-20KE MultiCore architecture can emulate custom state machines, FIFOs, and bus bridges with no NRE cost and full design re-spin flexibility. The 32,768-bit embedded SRAM (ESB) supports small FIFOs for bus protocol conversion such as PCI-to-local-bus or VME-to-PCI bridges. Dropped onto a legacy VME card, the FPGA converts signal levels and timing without disturbing the analog front-end design. The 144-LQFP package allows socketed or hand-reworked swap into existing through-hole ASIC footprints.
Recommandé
Military & Aerospace Retrofit Boards
The EP20K60ETC144-3N remains in demand for military/aerospace retrofit programs because long-life platforms (avionics, naval comms, ground radar) require form-fit-function replacement of aging Altera APEX-20KE parts. The 1.8V core and proven 0.22 µm CMOS process deliver stable performance across the commercial 0 °C to +85 °C range typical for sheltered equipment bays. The 144-LQFP gull-wing package withstands the mechanical rework and conformal-coating processes used in depot-level repairs. When newer Cyclone or Stratix devices are not form-fit compatible, the EP20K60ETC144-3N preserves the legacy BOM.
Recommandé
DSP Front-End Pre-Processing
The EP20K60ETC144-3N is used as a DSP front-end pre-processor because the 182 MHz internal frequency, 92 user I/Os, and dedicated clock networks allow sample-rate conversion, digital filtering, and FFT windowing before data reaches a host DSP or FPGA co-processor. The 32 Kbit embedded SRAM stores tap coefficients and small sample blocks. Deployed between an ADC and a Blackfin or TigerSHARC, the APEX-20KE offloads decimation and Hilbert transforms that would otherwise starve the DSP of bandwidth. The 144-LQFP pinout supports a wide parallel data bus plus JTAG debug access.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP20K60ETC144-3N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP20K60ETC144-3 | EP20K60ETC144-2N | EP20K60ETC144-2X | EP20K60ETC144-1X | EP20K60EFI144-2X | EP20K60EFC144-2XN |
|---|---|---|---|---|---|---|---|
| Package | 144-LQFP | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same | 144-LQFP - same |
| Brand | Intel (formerly Altera) | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera | Intel / Altera |
| Family | APEX-20KE | APEX-20KE | APEX-20KE | APEX-20KE | APEX-20KE | APEX-20KE | APEX-20KE |
| Speed Grade | -3 (fastest, ≈182 MHz) | -3 (≈182 MHz) | -2 (≈150 MHz) | -2 (≈150 MHz) | -1 (≈120 MHz) | -2 (≈150 MHz) | -2 (≈150 MHz) |
| Logic Elements | 2,560 | 2,560 | 2,560 | 2,560 | 2,560 | 2,560 | 2,560 |
| Typical Gate Count | 60K gates | 60K gates | 60K gates | 60K gates | 60K gates | 60K gates | 60K gates |
| Maximum User I/O | 92 | 92 | 92 | 92 | 92 | 92 | 92 |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Fastest speed grade in the APEX-20KE 144-LQFP family (vs EP20K60ETC144-2N)
- Lead-free finish designation ('N' suffix) matches modern Pb-free assembly lines (vs EP20K60ETC144-3)
- Highest internal frequency available in the 144-LQFP APEX-20KE form factor (vs EP20K60ETC144-1X)
Notes de conception
Estimated: at 50% logic utilization with all 92 I/Os toggling at 50 MHz on the EP20K60ETC144-3N, ICCINT draw is approximately 250–400 mA from the 1.8V rail. Provide at least four 0.1 µF ceramic decoupling capacitors placed adjacent to each VCCINT pin (pins 21, 55, 89, 129) plus a bulk 47 µF tantalum near the supply entry. Each VCCIO bank should have its own 0.1 µF + 10 µF decoupling pair to suppress switching noise on the I/O rails.
Route all four dedicated clock inputs (CLK0–CLK3, pins 30/31/64/65) as 50 Ω controlled-impedance traces with length matching within 100 mils if used in a DDR-style clock scheme. Keep JTAG chain signals (TDI/TMS/TCK/TDO on pins 98–101) away from switching I/O to avoid configuration corruption during in-system programming. The 144-LQFP 0.5 mm pitch requires NSMD pads with a 1:1.2 aperture ratio per Altera APEX-20KE design guidelines.
Estimated: the 144-LQFP EP20K60ETC144-3N has a typical θJA of approximately 35 °C/W on a 4-layer JEDEC test board with no airflow. At a worst-case 1.5W total dissipation (core + I/O), junction temperature rise above ambient is roughly 53 °C - acceptable within the 85 °C commercial ceiling for room-temperature operation, but a thermal relief copper pour under the package is recommended for sealed enclosures.
Do not use Quartus II versions newer than 13.0 sp1 to compile APEX-20KE designs - these device files were removed in later releases. Keep MAX+PLUS II 10.23 or Quartus II 13.0 sp1 installed in a VM or sandbox for legacy design maintenance. Configuration data stored in SRAM is volatile; the device must be reconfigured on every power-up via a serial PROM (EPC2) or via JTAG.
Informations de conformité
Lead-free ('N' suffix) per MPN code; RoHS, REACH and halogen-free status not explicitly confirmed in the verified web data and are marked unknown. AEC-Q100 is not applicable as this is a programmable logic device, not an automotive-grade IC.
