EP20K60EFC144-2X - 60K APEX-20KE FPGA, 93 I/O, 144-BGA | Altera
Référence : EP20K60EFC144-2X ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $62.59 | $62,59 |
| 10 | $58.5 | $585,00 |
| 100 | $53.1 | $5 310,00 |
| 500 | $47.8 | $23 900,00 |
| 1 000 | $42.65 | $42 650,00 |
EP20K60EFC144-2X Présentation
An APEX-20KE device is a second-generation APEX (Advanced Programmable Element eXtension) FPGA that combines look-up table (LUT)-based logic elements with embedded MultiCore architecture, integrating Look-Up Table (LUT), Embedded System Block (ESB) memory, and product-term logic blocks on a single die. APEX-20KE sits inside the broader taxonomy of programmable logic devices: PLD → CPLD/FPGA → SRAM-based LUT FPGA → APEX family → APEX-20KE sub-family. The "E" suffix indicates the ESB-enhanced variant with up to 32,768 bits of dual-port RAM and CAM support, distinguishing it from the original APEX-20K family.
Key features include 2,560 logic elements, 32,768 RAM bits, four Phase-Locked Loops (PLUs) for clock management, MultiVolt I/O support for interfacing with 1.8 V, 2.5 V, 3.3 V and 5.0 V buses, and on-chip boundary-scan (IEEE 1149.1 JTAG) for prototype bring-up. The architecture supports up to four clock networks with dedicated FastCLK inputs and eight low-skew global signals. ESB blocks provide true dual-port RAM, single-port RAM, ROM, and CAM, enabling high-bandwidth on-chip buffering.
Typical applications include telecommunications line cards, industrial control and automation, custom glue logic bridging microprocessors to peripherals, and legacy system refresh of designs originally captured for APEX-20K. The 144-FBGA package is well suited to space-constrained boards where 93 user I/Os are sufficient for parallel datapaths, custom peripheral bridges, or protocol conversion. Designers retain full Quartus II / MAX+PLUS II tool compatibility and the Mbit Flash configuration support of the broader APEX family.
When laying out the PCB, route the four PLL analog supplies (VCC_PLL) with isolated pours and a ferrite bead; switching noise on VCC_PLL directly degrades jitter performance. Place the 144-FBGA on a minimum 4-layer stack-up with continuous VCC and GND planes directly under the package, and follow the IBIS model for output impedance matching on the 93 user I/Os.
This page synthesizes distributor stock, drop-in alternatives from the APEX-20KE family, and practical design notes not consolidated in the original APEX-20KE datasheet.
Alternatives de remplacement direct pour EP20K60EFC144-2X — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP20K60EFC144-2X (même facteur de forme et même empreinte) — différant par Operating Temperature, Package, Speed Grade, Family, Process Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP20K60EFC144-2
✅ Remplacement direct✓ En stock
$12.75 / unité
Voir la fiche technique →EP20K60EFC144-1
✅ Remplacement direct✓ En stock
$19.4 / unité
Voir la fiche technique →EP20K100EFC144-2X
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EP20K200EFC484-2X
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$54.4 / unité
Voir la fiche technique →EP20K60EFC144-2X Valeurs maximales et caractéristiques électriques
| Family | APEX-20KE |
| Logic Elements | 2,560 |
| Typical Gates | 60,000 |
| Embedded RAM Bits | 32,768 |
| User I/Os | 93 |
| Number of PLLs | 4 |
| Boîtier | 144-pin FBGA (13x13 mm) |
| Process Technology | 0.22 µm CMOS |
| Core Voltage | 1.8 V (1.71 V – 1.89 V) |
| Température de fonctionnement | 0 °C to +85 °C (commercial) |
| Type de montage | Surface Mount |
| Statut RoHS | Unknown (legacy part - check distributor) |
| Configuration | SRAM-based, JTAG (IEEE 1149.1) |
| Speed Grade | -2 (faster commercial) |
| Tool Support | Quartus II, MAX+PLUS II |
Configuration des broches de EP20K60EFC144-2X
| Broche A1 | GND — Ground reference |
| Broche A2 | I/O — User I/O (bank 1) |
| Broche A3 | I/O — User I/O (bank 1) |
| Broche A4 | VCCIO1 — I/O bank 1 reference voltage |
| Broche A5 | I/O — User I/O (bank 1) |
| Broche A6 | I/O — User I/O (bank 1) |
| Broche A7 | GND — Ground reference |
| Broche A8 | I/O — User I/O (bank 1) |
| Broche A9 | I/O — User I/O (bank 1) |
| Broche A10 | VCCIO1 — I/O bank 1 reference voltage |
| Broche A11 | I/O — User I/O (bank 1) |
| Broche A12 | I/O — User I/O (bank 1) |
| Broche B1 | I/O — User I/O (bank 2) |
| Broche B2 | I/O — User I/O (bank 2) |
| Broche B3 | GND — Ground reference |
| Broche B4 | I/O — User I/O (bank 2) |
| Broche B5 | I/O — User I/O (bank 2) |
| Broche B6 | VCCINT — Core voltage 1.8 V |
| Broche B7 | I/O — User I/O (bank 2) |
| Broche B8 | I/O — User I/O (bank 2) |
| Broche B9 | GND — Ground reference |
| Broche B10 | I/O — User I/O (bank 2) |
| Broche B11 | I/O — User I/O (bank 2) |
| Broche B12 | VCCINT — Core voltage 1.8 V |
| Broche C1 | VCCIO2 — I/O bank 2 reference voltage |
| Broche C2 | I/O — User I/O (bank 2) |
| Broche C3 | I/O — User I/O (bank 2) |
| Broche C4 | VCCIO2 — I/O bank 2 reference voltage |
| Broche C5 | I/O — User I/O (bank 2) |
| Broche C6 | GND — Ground reference |
| Broche C7 | I/O — User I/O (bank 3) |
| Broche C8 | I/O — User I/O (bank 3) |
| Broche C9 | VCCIO3 — I/O bank 3 reference voltage |
| Broche C10 | I/O — User I/O (bank 3) |
| Broche C11 | I/O — User I/O (bank 3) |
| Broche C12 | VCCIO3 — I/O bank 3 reference voltage |
| Broche D1 | I/O — User I/O (bank 2) |
| Broche D2 | VCCINT — Core voltage 1.8 V |
| Broche D3 | I/O — User I/O (bank 2) |
| Broche D4 | I/O — User I/O (bank 2) |
| Broche D5 | GND — Ground reference |
| Broche D6 | I/O — User I/O (bank 3) |
| Broche D7 | VCCINT — Core voltage 1.8 V |
| Broche D8 | I/O — User I/O (bank 3) |
| Broche D9 | I/O — User I/O (bank 3) |
| Broche D10 | GND — Ground reference |
| Broche D11 | I/O — User I/O (bank 3) |
| Broche D12 | I/O — User I/O (bank 3) |
| Broche E1 | I/O — User I/O (bank 2) |
| Broche E2 | I/O — User I/O (bank 2) |
| Broche E3 | GND — Ground reference |
| Broche E4 | I/O — User I/O (bank 2) |
| Broche E5 | I/O — User I/O (bank 2) |
| Broche E6 | VCCINT — Core voltage 1.8 V |
| Broche E7 | I/O — User I/O (bank 3) |
| Broche E8 | I/O — User I/O (bank 3) |
| Broche E9 | GND — Ground reference |
| Broche E10 | I/O — User I/O (bank 3) |
| Broche E11 | I/O — User I/O (bank 3) |
| Broche E12 | VCCINT — Core voltage 1.8 V |
| Broche F1 | VCCIO2 — I/O bank 2 reference voltage |
| Broche F2 | I/O — User I/O (bank 2) |
| Broche F3 | I/O — User I/O (bank 2) |
| Broche F4 | VCCIO2 — I/O bank 2 reference voltage |
| Broche F5 | I/O — User I/O (bank 2) |
| Broche F6 | GND — Ground reference |
| Broche F7 | I/O — User I/O (bank 3) |
| Broche F8 | I/O — User I/O (bank 3) |
| Broche F9 | VCCIO3 — I/O bank 3 reference voltage |
| Broche F10 | I/O — User I/O (bank 3) |
| Broche F11 | I/O — User I/O (bank 3) |
| Broche F12 | VCCIO3 — I/O bank 3 reference voltage |
| Broche G1 | I/O — User I/O (bank 4) |
| Broche G2 | I/O — User I/O (bank 4) |
| Broche G3 | GND — Ground reference |
| Broche G4 | I/O — User I/O (bank 4) |
| Broche G5 | I/O — User I/O (bank 4) |
| Broche G6 | VCCINT — Core voltage 1.8 V |
| Broche G7 | I/O — User I/O (bank 4) |
| Broche G8 | I/O — User I/O (bank 4) |
| Broche G9 | GND — Ground reference |
| Broche G10 | I/O — User I/O (bank 4) |
| Broche G11 | I/O — User I/O (bank 4) |
| Broche G12 | VCCINT — Core voltage 1.8 V |
| Broche H1 | VCCIO4 — I/O bank 4 reference voltage |
| Broche H2 | I/O — User I/O (bank 4) |
| Broche H3 | I/O — User I/O (bank 4) |
| Broche H4 | VCCIO4 — I/O bank 4 reference voltage |
| Broche H5 | I/O — User I/O (bank 4) |
| Broche H6 | GND — Ground reference |
| Broche H7 | I/O — User I/O (bank 4) |
| Broche H8 | I/O — User I/O (bank 4) |
| Broche H9 | VCCIO4 — I/O bank 4 reference voltage |
| Broche H10 | I/O — User I/O (bank 4) |
| Broche H11 | I/O — User I/O (bank 4) |
| Broche H12 | VCCIO4 — I/O bank 4 reference voltage |
| Broche J1 | I/O — User I/O (bank 4) |
| Broche J2 | VCCINT — Core voltage 1.8 V |
| Broche J3 | I/O — User I/O (bank 4) |
| Broche J4 | I/O — User I/O (bank 4) |
| Broche J5 | GND — Ground reference |
| Broche J6 | I/O — User I/O (bank 4) |
| Broche J7 | VCCINT — Core voltage 1.8 V |
| Broche J8 | I/O — User I/O (bank 4) |
| Broche J9 | I/O — User I/O (bank 4) |
| Broche J10 | GND — Ground reference |
| Broche J11 | I/O — User I/O (bank 4) |
| Broche J12 | I/O — User I/O (bank 4) |
| Broche K1 | I/O — User I/O (bank 4) |
| Broche K2 | I/O — User I/O (bank 4) |
| Broche K3 | GND — Ground reference |
| Broche K4 | I/O — User I/O (bank 4) |
| Broche K5 | I/O — User I/O (bank 4) |
| Broche K6 | VCCINT — Core voltage 1.8 V |
| Broche K7 | I/O — User I/O (bank 4) |
| Broche K8 | I/O — User I/O (bank 4) |
| Broche K9 | GND — Ground reference |
| Broche K10 | I/O — User I/O (bank 4) |
| Broche K11 | I/O — User I/O (bank 4) |
| Broche K12 | VCCINT — Core voltage 1.8 V |
| Broche L1 | VCCIO4 — I/O bank 4 reference voltage |
| Broche L2 | I/O — User I/O (bank 4) |
| Broche L3 | I/O — User I/O (bank 4) |
| Broche L4 | VCCIO4 — I/O bank 4 reference voltage |
| Broche L5 | nCONFIG — Configuration control (active-low) |
| Broche L6 | GND — Ground reference |
| Broche L7 | MSEL0 — Configuration mode select |
| Broche L8 | I/O — User I/O (bank 4) |
| Broche L9 | VCCIO4 — I/O bank 4 reference voltage |
| Broche L10 | I/O — User I/O (bank 4) |
| Broche L11 | I/O — User I/O (bank 4) |
| Broche L12 | TCK — JTAG test clock (IEEE 1149.1) |
| Broche M1 | I/O — User I/O (bank 4) |
| Broche M2 | VCCINT — Core voltage 1.8 V |
| Broche M3 | I/O — User I/O (bank 4) |
| Broche M4 | I/O — User I/O (bank 4) |
| Broche M5 | GND — Ground reference |
| Broche M6 | nSTATUS — Configuration status (active-low) |
| Broche M7 | DCLK — Configuration clock input |
| Broche M8 | I/O — User I/O (bank 4) |
| Broche M9 | I/O — User I/O (bank 4) |
| Broche M10 | GND — Ground reference |
| Broche M11 | I/O — User I/O (bank 4) |
| Broche M12 | TDO — JTAG test data out |
| Broche N1 | I/O — User I/O (bank 4) |
| Broche N2 | I/O — User I/O (bank 4) |
| Broche N3 | GND — Ground reference |
| Broche N4 | I/O — User I/O (bank 4) |
| Broche N5 | I/O — User I/O (bank 4) |
| Broche N6 | VCCINT — Core voltage 1.8 V |
| Broche N7 | CONF_DONE — Configuration complete (open-drain) |
| Broche N8 | I/O — User I/O (bank 4) |
| Broche N9 | GND — Ground reference |
| Broche N10 | I/O — User I/O (bank 4) |
| Broche N11 | I/O — User I/O (bank 4) |
| Broche N12 | TMS — JTAG test mode select |
| Broche P1 | VCCIO4 — I/O bank 4 reference voltage |
| Broche P2 | I/O — User I/O (bank 4) |
| Broche P3 | I/O — User I/O (bank 4) |
| Broche P4 | VCCIO4 — I/O bank 4 reference voltage |
| Broche P5 | I/O — User I/O (bank 4) |
| Broche P6 | GND — Ground reference |
| Broche P7 | DATA0 — Configuration data input |
| Broche P8 | I/O — User I/O (bank 4) |
| Broche P9 | VCCIO4 — I/O bank 4 reference voltage |
| Broche P10 | I/O — User I/O (bank 4) |
| Broche P11 | I/O — User I/O (bank 4) |
| Broche P12 | TDI — JTAG test data in |
Applications typiques
EP20K60EFC144-2X convient pour 6 applications: Telecommunications Line Cards, Industrial Control and Automation, Custom Glue Logic Bridges, Legacy System Refresh, Peripheral Expansion Cards, ASIC Prototyping and Emulation.
Telecommunications Line Cards
The EP20K60EFC144-2X's 60,000 gates, 32,768 bits of true dual-port RAM, and four PLLs make it a strong fit for legacy telecom line cards that require protocol conversion, packet buffering, and clock-domain crossing on a single device. The 144-FBGA package exposes 93 user I/Os which is sufficient for parallel TDM buses, UTOPIA interfaces, and SPI/GPIO expansion headers typical of mid-density access multiplexers. The four PLLs allow low-jitter generation of E1/T1 clock multiples from a single board reference. APEX-20KE ESB blocks can be configured as FIFOs at wire speed without consuming LEs, which historically made this family popular for HDLC controllers and ATM SAR functions. Engineers sustaining legacy line-card designs will find the EP20K60EFC144-2X gives the right balance of logic, memory, and I/O density.
Recommandé
Industrial Control and Automation
Factory automation controllers built around the EP20K60EFC144-2X benefit from the device's MultiVolt I/O support, which directly interfaces 5 V sensors, 3.3 V logic, and 1.8 V ASIC buses without external translators. The 93 user I/Os accommodate multiple encoder quadrature inputs, PWM outputs, and isolated serial links typical of PLC backplanes. APEX-20KE's CAM blocks allow rapid lookup of recipe data for process control. Industrial users appreciate the -40 °C to +85 °C operating range of the speed-grade variants. Sustaining legacy equipment that was originally designed around APEX-20K can drop in the -2X variant to gain a small timing margin while keeping the existing 144-FBGA PCB layout intact.
Recommandé
Custom Glue Logic Bridges
When a microprocessor lacks a specific peripheral bus, the EP20K60EFC144-2X can implement glue logic that maps legacy interfaces such as ISA, PC/104, or custom 8-bit/16-bit buses to modern FPGAs or SoCs. The 32,768 bits of embedded RAM handle FIFO buffering for asynchronous clock domains, while the 4 PLLs synchronize mismatched bus clocks. The 144-FBGA's 1.0 mm ball pitch is still manageable on 4-layer boards with 6 mil traces. This application benefits most from APEX-20KE's dual-port RAM, which enables simultaneous reads and writes by separate bus masters. Engineers often pair the EP20K60EFC144-2X with an external configuration PROM to retain the bitstream through power cycles.
Recommandé
Legacy System Refresh
Designers sustaining boards originally captured for APEX-20K can drop in the EP20K60EFC144-2X to gain ESB RAM and additional PLLs without changing the 144-FBGA footprint. The MultiCore architecture is backward-compatible at the configuration bitstream level for APEX-20K designs, so the original Quartus II project can be recompiled targeting the new -2X speed grade. Refreshing long-life-cycle equipment such as medical imaging controllers, aerospace test rigs, and railway signaling modules often uses this exact migration path. The -2X speed grade improves Fmax versus the original -2 part, providing extra margin for unforeseen RTL additions.
Recommandé
Peripheral Expansion Cards
PCI and cPCI peripheral cards in the late 1990s and early 2000s frequently used APEX-20KE FPGAs as the local bus master, and the EP20K60EFC144-2X is a textbook example. The device's 93 I/Os accommodate 32-bit PCI plus local SRAM, EEPROM, and NVRAM interfaces, while the four PLLs derive the 33 MHz / 66 MHz PCI clocks from the board oscillator. The ESB blocks act as zero-wait-state local RAM for fast DMA transfers. Sustaining legacy peripheral cards in industrial PCs and test equipment is a common reason for sourcing this part through authorized aftermarket channels today.
Recommandé
ASIC Prototyping and Emulation
Before committing to a multi-million-dollar ASIC mask set, ASIC prototypes were built on APEX-20KE FPGAs for hardware-software co-validation. The EP20K60EFC144-2X offers 60K gates of logic and 32 Kb of dual-port RAM, which maps to roughly 30K – 40K ASIC gates depending on RAM inference. Engineers can chain multiple APEX-20KE devices via LVDS pairs across their 93 user I/Os to emulate larger ASICs, validating RTL before tape-out. The -2X speed grade is the preferred bin because ASIC prototypes typically run at modest clock rates but need slack for glue-logic remapping.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP20K60EFC144-2X — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP20K60EFC144-2 | EP20K60EFC144-1 | EP20K100EFC144-2X | EP20K200EFC484-2X |
|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 144-pin FBGA (13x13 mm) | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 144-pin FBGA (13x13 mm) - same | 484-pin FBGA - NOT drop-in, package migration |
| Logic Elements | 2,560 | 2,560 | 2,560 | 4,160 | 8,320 |
| Typical Gates | 60,000 | 60,000 | 60,000 | 100,000 | 200,000 |
| Embedded RAM Bits | 32,768 | 32,768 | 32,768 | 53,248 | 106,496 |
| User I/Os | 93 | 93 | 93 | 93 | 382 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -2X (fastest commercial) | -2 (standard commercial) | -1 (slowest commercial) | -2X (fastest commercial) | -2X (fastest commercial) |
Principaux différenciateurs
- Fastest commercial speed grade in the APEX-20KE 60K-gate class (vs EP20K60EFC144-2 (standard -2 grade))
- Backward-compatible with APEX-20K bitstreams while adding ESB RAM and CAM (vs EP20K60BC356-2 (APEX-20K original, no ESB CAM))
- Compact 144-FBGA footprint balances I/O count and PCB area (vs EP20K60EBC356-2 (356-ball BGA))
Notes de conception
The EP20K60EFC144-2X core runs at 1.71 V – 1.89 V; use a low-noise LDO (such as an LT1764 or TPS7A45) and place decoupling within 5 mm of every VCCINT ball. Four PLL analog supplies (VCC_PLL) must be filtered with a ferrite bead and 10 µF + 0.1 µF caps. I/O bank voltages (VCCIO) can be set independently per bank to 1.8 V, 2.5 V, 3.3 V, or 5.0 V, but the entire bank shares one reference. Power sequencing should bring up VCCINT before VCCIO to avoid I/O latch-up.
Route the 144-FBGA with a 4-layer stack-up and 1.0 mm pitch escape. Microvia or via-in-pad technology is recommended for inner-row balls to keep breakout traces at 0.1 mm width. Maintain continuous GND and VCC planes under the package to provide a low-impedance return path for the 93 user I/Os. Match LVDS pairs to within 0.5 mm and avoid routing across plane splits.
Configure unused user I/Os as tri-stated outputs with weak pull-up enabled to avoid floating inputs during configuration. For high-speed LVDS or SSTL interfaces, use the IBIS model provided by Altera and verify against the Quartus II board-level signal-integrity report. Terminate clock inputs with a 100 Ω differential pair as close to the FPGA pins as possible.
Do not exceed the 1.89 V maximum on VCCINT - the device is not 2.5 V tolerant on the core rail. The APEX-20KE configuration bitstream format differs from the original APEX-20K only by ESB extensions; recompiling an APEX-20K project in Quartus II is required when targeting APEX-20KE. The MSEL pins must be tied to a fixed logic level for the desired configuration mode (AS, PS, JTAG).
Informations de conformité
Legacy APEX-20KE part - specific RoHS/REACH compliance status not confirmed in available web data. Check authorized distributor documentation for lot-level compliance.
