eZ80F91AZ050SG - 50MHz 8-bit 256KB Flash MCU | Zilog
Référence : eZ80F91AZ050SG ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.4 | $164,00 |
| 100 | $13.95 | $1 395,00 |
| 500 | $12.2 | $6 100,00 |
| 1 000 | $10.85 | $10 850,00 |
eZ80F91AZ050SG Présentation
An 8-bit microcontroller (MCU) is a single-chip processor whose internal data path is 8 bits wide, optimized for control-oriented tasks that demand deterministic behaviour, low cost, and minimal power. The eZ80 architecture extends the classic Z80 instruction set with a 24-bit linear address space, making it a bridge between legacy 8-bit code and 32-bit addressing. Within the IC taxonomy it sits at: microcontroller -> embedded processor -> integrated circuit. It belongs to the broader class of flash microcontrollers and is commonly deployed in industrial control and embedded communication designs.
Key features include 32 general-purpose I/O pins, four 16-bit timers, a 10/100 Ethernet MAC with MII interface, two UARTs, I2C, SPI, IrDA encoder/decoder, and a JTAG debug port. The on-chip peripherals are designed for embedded internet connectivity, while the SRAM-backed Flash supports in-application programming for field upgrades.
The eZ80F91AZ050SG uses a single-cycle pipelined core running at 50 MHz, providing sustained throughput equivalent to 80 MIPS peak (Z80 instructions). The integrated EMAC implements full IEEE 802.3 MAC and PHY interfacing, eliminating the need for an external Ethernet controller in point-of-sale and embedded gateway designs.
Typical applications include industrial control, point-of-sale (POS) terminals, embedded communication gateways, security systems, and building automation. The wide address space makes the device attractive for legacy Z80 software migration and new 24-bit flat-memory designs.
Design considerations include ensuring proper decoupling on the analog supply pins, following the recommended 50 MHz crystal layout, and reviewing Zilog application note PS0192 for EMAC magnetics and PHY interface. The device operates from a 3.3 V supply.
This page consolidates verified distributor pricing, drop-in Zilog alternatives, and application guidance not collated in the standalone datasheet, providing an integrated reference for embedded engineers.
Alternatives de remplacement direct pour eZ80F91AZ050SG — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec eZ80F91AZ050SG (même facteur de forme et même empreinte) — différant par Package, UART, Core Architecture, Ethernet MAC, Operating Temperature.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EZ80F91AZ050EG
✅ Remplacement direct✓ En stock
$11.85 / unité
Voir la fiche technique →EZ80F92AZ050EG
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
eZ80F91AZ050SG
✅ Remplacement direct✓ En stock
$10.85 / unité
Voir la fiche technique →eZ80F91AZ050SG Valeurs maximales et caractéristiques électriques
| Product Family | eZ80 Acclaim! |
| Core | eZ80 (8-bit Z80-compatible) |
| Fréquence d'horloge maximale | 50 MHz |
| Program Memory (Flash) | 256 KB (256K x 8) |
| SRAM | 16 KB |
| External Memory Support | 16 MB (24-bit addressing) |
| Operating Voltage | 3.3 V (typical) |
| General-Purpose I/O | 32 |
| 16-bit Timers | 4 |
| Ethernet MAC (EMAC) | Yes (10/100 with MII) |
| UART | 2 |
| I2C / SPI | Yes |
| IrDA Encoder/Decoder | Yes |
| Boîtier | 144-LQFP (20x20 mm) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
Configuration des broches de eZ80F91AZ050SG
| Broche 1 | PA0 — Port A bit 0 / GPIO |
| Broche 2 | PA1 — Port A bit 1 / GPIO |
| Broche 3 | PA2 — Port A bit 2 / GPIO |
| Broche 4 | PA3 — Port A bit 3 / GPIO |
| Broche 5 | PA4 — Port A bit 4 / GPIO |
| Broche 6 | PA5 — Port A bit 5 / GPIO |
| Broche 7 | PA6 — Port A bit 6 / GPIO |
| Broche 8 | PA7 — Port A bit 7 / GPIO |
| Broche 9 | VSS — Ground |
| Broche 10 | VDD — 3.3 V core supply |
| Broche 11 | PB0 — Port B bit 0 / GPIO |
| Broche 12 | PB1 — Port B bit 1 / GPIO |
| Broche 13 | PB2 — Port B bit 2 / GPIO |
| Broche 14 | PB3 — Port B bit 3 / GPIO |
| Broche 15 | PB4 — Port B bit 4 / GPIO |
| Broche 16 | PB5 — Port B bit 5 / GPIO |
| Broche 17 | PB6 — Port B bit 6 / GPIO |
| Broche 18 | PB7 — Port B bit 7 / GPIO |
| Broche 19 | VSS — Ground |
| Broche 20 | VDD — 3.3 V core supply |
| Broche 21 | PC0 — Port C bit 0 / GPIO |
| Broche 22 | PC1 — Port C bit 1 / GPIO |
| Broche 23 | PC2 — Port C bit 2 / GPIO |
| Broche 24 | PC3 — Port C bit 3 / GPIO |
| Broche 25 | PC4 — Port C bit 4 / GPIO |
| Broche 26 | PC5 — Port C bit 5 / GPIO |
| Broche 27 | PC6 — Port C bit 6 / GPIO |
| Broche 28 | PC7 — Port C bit 7 / GPIO |
| Broche 29 | VSS — Ground |
| Broche 30 | VDD — 3.3 V core supply |
| Broche 31 | PD0 — Port D bit 0 / GPIO |
| Broche 32 | PD1 — Port D bit 1 / GPIO |
| Broche 33 | PD2 — Port D bit 2 / GPIO |
| Broche 34 | PD3 — Port D bit 3 / GPIO |
| Broche 35 | PD4 — Port D bit 4 / GPIO |
| Broche 36 | PD5 — Port D bit 5 / GPIO |
| Broche 37 | PD6 — Port D bit 6 / GPIO |
| Broche 38 | PD7 — Port D bit 7 / GPIO |
| Broche 39 | VSS — Ground |
| Broche 40 | VDD — 3.3 V core supply |
| Broche 41 | TXD0 — UART0 transmit |
| Broche 42 | RXD0 — UART0 receive |
| Broche 43 | TXD1 — UART1 transmit |
| Broche 44 | RXD1 — UART1 receive |
| Broche 45 | SCL — I2C clock |
| Broche 46 | SDA — I2C data |
| Broche 47 | SCK — SPI clock |
| Broche 48 | MOSI — SPI master-out / slave-in |
| Broche 49 | MISO — SPI master-in / slave-out |
| Broche 50 | SS — SPI slave select |
| Broche 51 | VSS — Ground |
| Broche 52 | VDD — 3.3 V core supply |
| Broche 53 | TCLK0 — Timer 0 clock input |
| Broche 54 | TCLK1 — Timer 1 clock input |
| Broche 55 | TCLK2 — Timer 2 clock input |
| Broche 56 | TCLK3 — Timer 3 clock input |
| Broche 57 | PWM0 — Timer 0 PWM output |
| Broche 58 | PWM1 — Timer 1 PWM output |
| Broche 59 | PWM2 — Timer 2 PWM output |
| Broche 60 | PWM3 — Timer 3 PWM output |
| Broche 61 | VSS — Ground |
| Broche 62 | VDD — 3.3 V core supply |
| Broche 63 | TXCLK — EMAC transmit clock (MII) |
| Broche 64 | TXEN — EMAC transmit enable (MII) |
| Broche 65 | TXD_0 — EMAC transmit data 0 (MII) |
| Broche 66 | TXD_1 — EMAC transmit data 1 (MII) |
| Broche 67 | TXD_2 — EMAC transmit data 2 (MII) |
| Broche 68 | TXD_3 — EMAC transmit data 3 (MII) |
| Broche 69 | VSS — Ground |
| Broche 70 | VDD — 3.3 V core supply |
| Broche 71 | RXCLK — EMAC receive clock (MII) |
| Broche 72 | RXDV — EMAC receive data valid (MII) |
| Broche 73 | RXD_0 — EMAC receive data 0 (MII) |
| Broche 74 | RXD_1 — EMAC receive data 1 (MII) |
| Broche 75 | RXD_2 — EMAC receive data 2 (MII) |
| Broche 76 | RXD_3 — EMAC receive data 3 (MII) |
| Broche 77 | VSS — Ground |
| Broche 78 | VDD — 3.3 V core supply |
| Broche 79 | CRS — EMAC carrier sense (MII) |
| Broche 80 | COL — EMAC collision detect (MII) |
| Broche 81 | MDC — EMAC management data clock |
| Broche 82 | MDIO — EMAC management data I/O |
| Broche 83 | VSS — Ground |
| Broche 84 | VDD — 3.3 V core supply |
| Broche 85 | IRTX — IrDA transmit |
| Broche 86 | IRRX — IrDA receive |
| Broche 87 | TDI — JTAG test data in |
| Broche 88 | TDO — JTAG test data out |
| Broche 89 | TMS — JTAG test mode select |
| Broche 90 | TCK — JTAG test clock |
| Broche 91 | TRST — JTAG test reset |
| Broche 92 | VSS — Ground |
| Broche 93 | VDD — 3.3 V core supply |
| Broche 94 | A0 — Address bus bit 0 |
| Broche 95 | A1 — Address bus bit 1 |
| Broche 96 | A2 — Address bus bit 2 |
| Broche 97 | A3 — Address bus bit 3 |
| Broche 98 | A4 — Address bus bit 4 |
| Broche 99 | A5 — Address bus bit 5 |
| Broche 100 | A6 — Address bus bit 6 |
| Broche 101 | A7 — Address bus bit 7 |
| Broche 102 | VSS — Ground |
| Broche 103 | VDD — 3.3 V core supply |
| Broche 104 | A8 — Address bus bit 8 |
| Broche 105 | A9 — Address bus bit 9 |
| Broche 106 | A10 — Address bus bit 10 |
| Broche 107 | A11 — Address bus bit 11 |
| Broche 108 | A12 — Address bus bit 12 |
| Broche 109 | A13 — Address bus bit 13 |
| Broche 110 | A14 — Address bus bit 14 |
| Broche 111 | A15 — Address bus bit 15 |
| Broche 112 | VSS — Ground |
| Broche 113 | VDD — 3.3 V core supply |
| Broche 114 | D0 — Data bus bit 0 |
| Broche 115 | D1 — Data bus bit 1 |
| Broche 116 | D2 — Data bus bit 2 |
| Broche 117 | D3 — Data bus bit 3 |
| Broche 118 | D4 — Data bus bit 4 |
| Broche 119 | D5 — Data bus bit 5 |
| Broche 120 | D6 — Data bus bit 6 |
| Broche 121 | D7 — Data bus bit 7 |
| Broche 122 | VSS — Ground |
| Broche 123 | VDD — 3.3 V core supply |
| Broche 124 | RD — External memory read strobe |
| Broche 125 | WR — External memory write strobe |
| Broche 126 | CS0 — Chip select 0 |
| Broche 127 | CS1 — Chip select 1 |
| Broche 128 | CS2 — Chip select 2 |
| Broche 129 | CS3 — Chip select 3 |
| Broche 130 | VSS — Ground |
| Broche 131 | VDD — 3.3 V core supply |
| Broche 132 | RESET — Active-low reset input |
| Broche 133 | NMI — Non-maskable interrupt |
| Broche 134 | XTAL1 — Crystal oscillator input |
| Broche 135 | XTAL2 — Crystal oscillator output |
| Broche 136 | VSS — Ground |
| Broche 137 | VDD — 3.3 V core supply |
| Broche 138 | PE0 — Port E bit 0 / GPIO |
| Broche 139 | PE1 — Port E bit 1 / GPIO |
| Broche 140 | PE2 — Port E bit 2 / GPIO |
| Broche 141 | PE3 — Port E bit 3 / GPIO |
| Broche 142 | PE4 — Port E bit 4 / GPIO |
| Broche 143 | PE5 — Port E bit 5 / GPIO |
| Broche 144 | PE6 — Port E bit 6 / GPIO |
Applications typiques
eZ80F91AZ050SG convient pour 6 applications: Point-of-Sale (POS) Terminals, Industrial Control & Gateways, Embedded Communication / Networked Sensors, Security & Access Control Panels, Building Automation Controllers, Legacy Z80 System Migration.
Point-of-Sale (POS) Terminals
The eZ80F91AZ050SG is purpose-built for POS terminal designs thanks to its integrated 10/100 EMAC with MII and dual UART interfaces. The 50 MHz eZ80 core executes TCP/IP stacks and payment-protocol firmware directly on-chip, while the 256 KB Flash stores terminal application code and the 16 KB SRAM buffers network packets during transactions. The 144-LQFP (20x20 mm) package supports compact terminal enclosures and the Z80-compatible core simplifies migration of legacy POS firmware. Designers pair the eZ80F91 with external PHYs (such as DP83848) and secure Flash memories (DS28E25) to build IEC 60950-compliant payment systems.
Recommandé
Industrial Control & Gateways
In industrial control and embedded gateway applications, the eZ80F91AZ050SG serves as a networked controller bridging fieldbus sensors to Ethernet backbones. Its integrated EMAC provides deterministic 10/100 connectivity, while the two UARTs support RS-232/RS-485 fieldbus masters for Modbus RTU or proprietary protocols. The four 16-bit timers generate PWM outputs for actuator control, and the 32 GPIO handle digital sensor inputs and relay drivers. With 256 KB Flash and 24-bit addressing, the device runs full Modbus TCP and EtherNet/IP gateway firmware while the 144-LQFP package offers robust thermal performance for industrial temperature operation.
Recommandé
Embedded Communication / Networked Sensors
The eZ80F91AZ050SG is ideal for networked embedded communication devices such as environmental sensor hubs, building automation controllers, and remote telemetry units. The 50 MHz core processes TCP/IP, UDP, and lightweight HTTP/MQTT stacks on-chip, while the integrated EMAC delivers full 10/100 Ethernet speeds without an external MAC. The 32 GPIO handle digital sensor interfaces and the four 16-bit timers manage periodic sampling and watchdog functions. With its wide 24-bit address space, the device can buffer large data payloads before forwarding, and the Z80-compatible instruction set allows legacy sensor firmware to be reused directly.
Recommandé
Security & Access Control Panels
The eZ80F91AZ050SG is well matched to security and access-control panel designs that need on-board networking combined with digital I/O for door strikes, keypads, and alarm sensors. The integrated EMAC provides IP-based reporting to central monitoring stations, while the dual UARTs support legacy keypads and serial card readers. The 256 KB Flash stores event logs and credential databases, and the 16 KB SRAM buffers real-time alarm events. Designers pair the eZ80F91 with secure authenticators like DS28E25 for tamper detection and with RTC devices like DS1307N for time-stamped audit trails.
Recommandé
Building Automation Controllers
In building automation designs the eZ80F91AZ050SG acts as a BACnet/Modbus gateway node controlling HVAC, lighting, and access subsystems. The 50 MHz eZ80 core runs BACnet/IP stacks with the integrated EMAC, while the two UARTs handle Modbus RTU side-chains for legacy HVAC equipment. The 32 GPIO drive relay outputs for lighting and read digital inputs from thermostats and motion sensors. The 144-LQFP package supports compact DIN-rail enclosure designs, and the wide 24-bit address space allows direct memory-mapped access to large configuration databases used by modern building automation protocols.
Recommandé
Legacy Z80 System Migration
The eZ80F91AZ050SG is the natural drop-in migration target for legacy Z80 systems needing 16 MB address space and integrated Ethernet. Existing Z80 firmware runs in Z80-compatible mode at 50 MHz with a single-cycle pipelined core, while new code can use the 24-bit flat-memory model. The 256 KB Flash supports in-application firmware updates for field-deployed legacy systems, and the 144-LQFP package simplifies migration to surface-mount manufacturing. Engineers pair the eZ80F91 with the same EMAC PHYs used in modern designs to extend the lifecycle of industrial Z80 product lines without full firmware rewrites.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour eZ80F91AZ050SG — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EZ80F91AZ050EG | EZ80F92AZ050EG |
|---|---|---|---|
| Package | 144-LQFP (20x20 mm) | 144-LQFP (20x20 mm) - same | 144-LQFP (20x20 mm) - same |
| Brand | Zilog | Zilog | Zilog |
| Maximum Clock Frequency | 50 MHz | 50 MHz | 50 MHz |
| Flash Memory | 256 KB | 256 KB | 128 KB |
| SRAM | 16 KB | 16 KB | 16 KB |
| Ethernet MAC (EMAC) | Yes (10/100 MII) | Yes (10/100 MII) | Yes (10/100 MII) |
| GPIO Count | 32 | 32 | 32 |
| Lead-Free Finish | Standard SnPb (SG) | Yes - lead-free / RoHS (EG) | Yes - lead-free / RoHS (EG) |
Principaux différenciateurs
- Integrated 10/100 Ethernet MAC with MII (vs EZ80F92AZ050EG)
- 256 KB Flash vs 128 KB on F92 (vs EZ80F92AZ050EG)
- Lead-free RoHS-compliant option available (vs EZ80F91AZ050EG)
Notes de conception
Decouple each VDD/VSS pair with a 100 nF ceramic capacitor placed within 5 mm of the package pin, plus a 10 uF bulk capacitor near the IC. The eZ80F91AZ050SG core draws transient current during EMAC packet transmission, and insufficient decoupling can cause brown-out resets. Per Zilog PS0192 design guidance, place a ferrite bead between the analog and digital supplies if the EMAC MII lines run near sensitive analog traces.
Route the EMAC MII traces (TXCLK, TXEN, TXD_0..3, RXCLK, RXDV, RXD_0..3, CRS, COL, MDC, MDIO) with matched 50 ohm controlled impedance and length matching within 25 mil. The MII bus runs at 25 MHz, so keep traces on a single inner layer with continuous ground plane beneath. Place the external PHY (e.g. DP83848) within 50 mm of the eZ80F91 to meet MII timing budgets per IEEE 802.3.
Do not exceed 3.6 V on any VDD rail or the on-chip regulator will be destroyed. The XTAL1/XTAL2 pins require a fundamental-mode crystal with load capacitors matched to the crystal specification (typically 18-22 pF). Driving RESET low for less than the minimum 4 clock cycles will not fully reset the eZ80 core; follow PS0192 reset timing. When migrating from Z80 mode to 24-bit ADL mode, ensure interrupt vectors are remapped or unexpected behaviour will occur.
At 50 MHz clock the eZ80F91AZ050SG core power dissipation is approximately 0.5 W typical. The 144-LQFP (20x20 mm) package provides adequate thermal dissipation with a minimum 4-layer PCB copper pour of at least 1 square inch under the exposed pad area. For industrial temperature operation, derate clock speed to 40 MHz above 85 C ambient to keep junction temperature within the 125 C limit.
Informations de conformité
Standard (SG) finish is original terminal finish; lead-free EG variant is required for RoHS compliance. AEC-Q100 not applicable for industrial networking MCUs.
