CYUSB3013-BZXC - EZ-USB FX3 USB 3.2 Gen 1 Controller | Infineon
Référence : CYUSB3013-BZXC ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $35.2 | $352,00 |
| 100 | $31.85 | $3 185,00 |
| 500 | $28.1 | $14 050,00 |
| 1 000 | $24.75 | $24 750,00 |
CYUSB3013-BZXC Présentation
A USB 3.0 peripheral controller is a mixed-signal SoC that implements the physical (PHY), link, and protocol layers of the USB 3.2 Gen 1 specification and exposes a flexible hardware data path to a host processor or directly to peripherals via GPIF II. Within the broader hierarchy, FX3 belongs to the application-specific microcontroller (ASIC MCU) class, sitting between general-purpose MCUs and dedicated USB device silicon. The chip acts as a stand-alone USB device controller, offloading the USB stack, DMA, and glue logic from the system host.
Key differentiating features of the CYUSB3013-BZXC include USB 3.1 Gen 1 and USB 2.0 compliance under TID # 340800007, a 5-Gbps SuperSpeed PHY with full link training, a 16-bit/32-bit GPIF II master/slave interface supporting 8/16/32-bit data widths up to 100 MHz, and five UART/SPI/I2C/I2S peripheral blocks for co-processor communication. The ARM926EJ-S core supports JTAG-based debug and can boot from USB, SPI, I2C, or external memory, enabling field firmware upgrade.
Typical end-use scenarios for the CYUSB3013-BZXC include USB 3.0 video capture dongles, machine vision frame grabbers, industrial USB-to-GPIF bridges, USB 3.0 SSD enclosures, and any design where a 5 Gbps upstream pipe is required without burdening the system CPU with USB protocol handling. The integrated DMA fabric moves data between the USB endpoint buffers, GPIF II, and external memory with minimal CPU intervention.
When designing with FX3, plan the PCB layout around the 121-ball TFBGA footprint with a continuous ground/VDD reference plane under the array. Decoupling must include bulk 4.7 uF plus 0.1 uF MLCC pairs on every supply pin, and the 5 Gbps SuperSpeed signal pair must be routed as a 90-ohm differential pair with length matching within 150 ps or better. Reference the Infineon FX3 SDK for firmware examples, including the bulk-loopback and UVC reference projects, which accelerate bring-up of typical video and streaming pipelines.
Alternatives de remplacement direct pour CYUSB3013-BZXC — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
CYUSB3035-BZXI
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CYUSB3014-BZXC
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CYUSB3023-BZXC
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
CYUSB3013-BZXI
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
CYUSB3035-BZXC
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
CYUSB3023-BZXI
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
CYUSB3013-BZXC Valeurs maximales et caractéristiques électriques
| USB Standard | USB 3.1 Gen 1 / USB 2.0 (TID # 340800007) |
| USB PHY Speed | 5 Gbps SuperSpeed |
| Processor Core | ARM926EJ-S |
| Core Frequency | up to 200 MHz |
| On-chip SRAM | 512 KB |
| External Memory Bus | 16-bit, up to 200 MHz |
| GPIF II Width | 8/16/32-bit selectable |
| GPIF II Frequency | up to 100 MHz |
| Boîtier | 121-TFBGA, 10x10 mm |
| Supply Voltage (Core) | 1.2 V |
| Supply Voltage (I/O) | 1.8 V to 3.3 V |
| Température de fonctionnement | 0 C to +70 C (commercial) |
| Boot Sources | USB, SPI, I2C, parallel flash |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
Configuration des broches de CYUSB3013-BZXC
| Broche A1 | GND — Common ground reference |
| Broche A2 | USB_DP — USB 2.0 D+ data line |
| Broche A3 | USB_DM — USB 2.0 D- data line |
| Broche A4 | VDD_IO — I/O supply 1.8 V to 3.3 V |
| Broche B1 | GND — Common ground reference |
| Broche B2 | VDD_PHY — USB PHY analog supply |
| Broche B3 | USB3_TX_DP — USB 3.0 SuperSpeed transmit D+ |
| Broche B4 | USB3_TX_DM — USB 3.0 SuperSpeed transmit D- |
| Broche C1 | VDD_CORE — Core supply 1.2 V |
| Broche C2 | USB3_RX_DP — USB 3.0 SuperSpeed receive D+ |
| Broche C3 | USB3_RX_DM — USB 3.0 SuperSpeed receive D- |
| Broche C4 | RESET — Active-low chip reset |
| Broche D1 | GPIF_DQ0 — GPIF II data bit 0 |
| Broche D2 | GPIF_DQ8 — GPIF II data bit 8 |
| Broche D3 | GPIF_CTL0 — GPIF II control bit 0 |
| Broche D4 | GPIF_CTL4 — GPIF II control bit 4 |
| Broche E1 | GPIF_DQ1 — GPIF II data bit 1 |
| Broche E2 | GPIF_DQ9 — GPIF II data bit 9 |
| Broche E3 | GPIF_CTL1 — GPIF II control bit 1 |
| Broche E4 | GPIF_CTL5 — GPIF II control bit 5 |
| Broche F1 | GPIF_DQ2 — GPIF II data bit 2 |
| Broche F2 | GPIF_DQ10 — GPIF II data bit 10 |
| Broche F3 | GPIF_CTL2 — GPIF II control bit 2 |
| Broche F4 | GPIF_CTL6 — GPIF II control bit 6 |
| Broche G1 | GPIF_DQ3 — GPIF II data bit 3 |
| Broche G2 | GPIF_DQ11 — GPIF II data bit 11 |
| Broche G3 | GPIF_CTL3 — GPIF II control bit 3 |
| Broche G4 | GPIF_CTL7 — GPIF II control bit 7 |
| Broche H1 | GPIF_DQ4 — GPIF II data bit 4 |
| Broche H2 | GPIF_DQ12 — GPIF II data bit 12 |
| Broche H3 | GPIF_PCLK — GPIF II peripheral clock |
| Broche H4 | GND — Common ground reference |
| Broche J1 | GPIF_DQ5 — GPIF II data bit 5 |
| Broche J2 | GPIF_DQ13 — GPIF II data bit 13 |
| Broche J3 | GPIF_PRDY — GPIF II peripheral ready |
| Broche J4 | VDD_IO — I/O supply 1.8 V to 3.3 V |
| Broche K1 | GPIF_DQ6 — GPIF II data bit 6 |
| Broche K2 | GPIF_DQ14 — GPIF II data bit 14 |
| Broche K3 | UART_CTS — UART clear-to-send (manufacturing test) |
| Broche K4 | UART_RTS — UART request-to-send (manufacturing test) |
| Broche L1 | GPIF_DQ7 — GPIF II data bit 7 |
| Broche L2 | GPIF_DQ15 — GPIF II data bit 15 |
| Broche L3 | I2C_SCL — I2C clock for boot / peripherals |
| Broche L4 | I2C_SDA — I2C data for boot / peripherals |
| Broche M1 | VDD_CORE — Core supply 1.2 V |
| Broche M2 | SPI_SCK — SPI clock for boot flash |
| Broche M3 | SPI_SSN — SPI slave select for boot flash |
| Broche M4 | SPI_MISO — SPI master-in slave-out |
| Broche N1 | GND — Common ground reference |
| Broche N2 | SPI_MOSI — SPI master-out slave-in |
| Broche N3 | JTAG_TCK — JTAG test clock |
| Broche N4 | JTAG_TMS — JTAG test mode select |
| Broche P1 | VDD_IO — I/O supply 1.8 V to 3.3 V |
| Broche P2 | JTAG_TDI — JTAG test data in |
| Broche P3 | JTAG_TDO — JTAG test data out |
| Broche P4 | JTAG_TRST — JTAG test reset (active low) |
| Broche R1 | GND — Common ground reference |
| Broche R2 | FSLC[0] — Boot mode selection bit 0 |
| Broche R3 | FSLC[1] — Boot mode selection bit 1 |
| Broche R4 | FSLC[2] — Boot mode selection bit 2 |
| Broche T1 | GND — Common ground reference |
| Broche T2 | PMODE[0] — USB 3.0/2.0 mode control bit 0 |
| Broche T3 | PMODE[1] — USB 3.0/2.0 mode control bit 1 |
| Broche T4 | PMODE[2] — USB 3.0/2.0 mode control bit 2 |
| Broche U1 | VDD_CORE — Core supply 1.2 V |
| Broche U2 | GND — Common ground reference |
| Broche U3 | VBUS — USB VBUS detect input |
| Broche U4 | VDD_IO — I/O supply 1.8 V to 3.3 V |
Applications typiques
CYUSB3013-BZXC convient pour 6 applications: USB 3.0 Video Capture Dongle, Machine Vision Frame Grabber, USB 3.0 SSD Enclosure, USB to GPIF II Bridge, Industrial USB Test and Measurement Probe, USB 3.0 Medical Imaging Capture.
USB 3.0 Video Capture Dongle
The CYUSB3013-BZXC fits USB 3.0 video capture dongles because its 5 Gbps SuperSpeed PHY and on-chip DMA fabric sustain uncompressed 1080p60 streaming without host CPU load. The GPIF II interface accepts an external HDMI receiver or MIPI-to-parallel bridge, then transfers pixel data over USB bulk endpoints at 3-4 Gbps. The integrated ARM926EJ-S handles USB enumeration and UVC class requests while the DMA engine streams pixels to the host. PC drops into a UVC firmware example from the Infineon FX3 SDK to accelerate bring-up; power dissipation is roughly 0.6 W at full SuperSpeed streaming, manageable without heatsinking at the 121-TFBGA 10x10 mm footprint.
Recommandé
Machine Vision Frame Grabber
The CYUSB3013-BZXC suits machine vision frame grabbers because its GPIF II master interface supports 32-bit parallel image sensors at 100 MHz, yielding 400 MB/s of sensor data. PC the 16-bit external memory bus buffers intermediate frames; the on-chip DMA engine then streams processed frames over USB 3.0 to a host PC for OpenCV or AI inference. PC the 200 MHz ARM926EJ-S offloads image pre-processing such as color-space conversion. According to the FX3 datasheet, the GPIF II Designer tool exports state-machine firmware for CameraLink-style sensors. The 121-TFBGA package fits inside a USB3 Vision-compliant housing with adequate thermal relief at typical 1-2 W dissipation.
Recommandé
USB 3.0 SSD Enclosure
The CYUSB3013-BZXC fits USB 3.0 SSD enclosures because its 5 Gbps USB pipe saturates SATA III SSDs without bottlenecking. The GPIF II master interface connects to a SATA-to-parallel bridge or directly to a NAND controller with 16-bit/32-bit data widths. PC the integrated ARM926EJ-S handles USB Mass Storage class requests and SCSI command translation; the DMA engine moves blocks between USB endpoints and the SATA controller at line-rate. PC the 512 KB on-chip SRAM holds descriptor tables plus short command queues. According to the FX3 SDK, the USB-SATA reference design reaches 380 MB/s read throughput over UASP. The 1.2 V core / 1.8 V-3.3 V I/O supplies simplify shared-rail designs with SATA bridge ICs.
Recommandé
USB to GPIF II Bridge
The CYUSB3013-BZXC is the canonical solution for a USB-to-GPIF II bridge because the GPIF II hardware waveform generator is on-die, eliminating the need for an external FPGA. PC designers describe the timing diagram once in the GPIF II Designer tool, and the chip replays it deterministically against any 8/16/32-bit peripheral. PC the on-chip DMA engine pumps bulk data at 3.2 GB/s sustained from the peripheral to the USB host. According to the Infineon hardware manual, common bridge targets are ADC/DAC front-ends, custom sensors, and FPGA data sinks. The 121-TFBGA package plus external 16-bit SRAM gives a compact, low-cost bridge solution.
Recommandé
Industrial USB Test and Measurement Probe
The CYUSB3013-BZXC fits industrial USB test probes because its ARM926EJ-S can post-process measurements on-chip while the GPIF II streams raw samples from the ADC. PC 200 MHz ARM926EJ-S handles FFT, averaging, and protocol decoding; the 16-bit external memory bus holds capture buffers; the 512 KB on-chip SRAM holds descriptor tables. PC the USB Test & Measurement Class (USBTMC) firmware from the FX3 SDK turns the device into a SCPI-compatible instrument. According to the FX3 datasheet, sustained 4 Gbps bulk streaming works well for 12-bit ADC sampling at 200 MSPS. Industrial temp variant CYUSB3035-BZXI is recommended for -40C to +85C deployment.
Recommandé
USB 3.0 Medical Imaging Capture
The CYUSB3013-BZXC suits USB 3.0 medical imaging capture because it sustains 5 Gbps uncompressed streams from ultrasound front-ends and endoscopes. PC the on-chip DMA engine transfers pixel data from the GPIF II port to USB bulk endpoints at line-rate, with zero CPU intervention, reducing latency and jitter for real-time diagnostics. PC the ARM926EJ-S handles USB enumeration, class-specific commands, and image preprocessing. According to Infineon documentation, the medical imaging reference design transfers 4K endoscopy frames at 30 fps over UVC. The 1.2 V core supply and 0 C to +70 C commercial temperature range cover most clinical room environments.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour CYUSB3013-BZXC — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | CYUSB3035-BZXI | CYUSB3014-BZXC | CYUSB3023-BZXC | CYUSB3035-BZXC |
|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | 121-TFBGA, 10x10 mm | 121-TFBGA, 10x10 mm | 121-TFBGA, 10x10 mm | 121-TFBGA, 10x10 mm | 121-TFBGA, 10x10 mm |
| On-chip SRAM | 512 KB | 512 KB | 128 KB | 256 KB | 512 KB |
| USB Standard | USB 3.1 Gen 1 + USB 2.0 | USB 3.1 Gen 1 + USB 2.0 | USB 3.1 Gen 1 + USB 2.0 | USB 3.1 Gen 1 + USB 2.0 | USB 3.1 Gen 1 + USB 2.0 |
| Core Frequency | up to 200 MHz | up to 200 MHz | up to 200 MHz | up to 200 MHz | up to 200 MHz |
| GPIF II Width | 8/16/32-bit | 8/16/32-bit | 8/16/32-bit | 8/16/32-bit | 8/16/32-bit |
| Operating Temperature | 0 C to +70 C | -40 C to +85 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Charger Detect Output | Yes | No | Yes | Yes | No |
Principaux différenciateurs
- Largest on-chip SRAM in the FX3 family (vs CYUSB3023-BZXC)
- Retains charger-detect output for USB BC 1.2 compliance (vs CYUSB3035-BZXI)
- Full 32-bit GPIF II master bus at 100 MHz (vs CYUSB3014-BZXC)
Notes de conception
Use a continuous ground reference plane on layer 2 directly under the 121-TFBGA footprint, with stitch vias around the perimeter every 1-2 mm to control return-current paths. Route the 5 Gbps SuperSpeed differential pair (USB3_TX_DP/DM and USB3_RX_DP/DM) as a 90-ohm differential with intra-pair skew under 1 ps and length matching within 150 ps. Keep the SuperSpeed pair at least 4x dielectric thickness (>=0.4 mm) away from any other high-speed signal to minimize crosstalk.
Decouple every supply pin with a 0.1 uF X7R MLCC placed within 1 mm of the pin plus a 4.7 uF bulk capacitor within 5 mm. Tie VDD_CORE (1.2 V) and VDD_IO (1.8 V-3.3 V) on independent LDO outputs and add a ferrite bead between the USB PHY analog supply VDD_PHY and the digital 1.2 V rail. According to the FX3 hardware manual, peak transient current on VDD_CORE can reach 250 mA during SuperSpeed link training - a 4.7 uF bulk cap prevents rail collapse.
Configure FSLC[2:0] and PMODE[2:0] strapping pins to the correct boot mode before power-up; incorrect strapping causes the device to enumerate as USB 2.0 only or fail to boot from SPI. Do not leave unused GPIF II data bits floating - tie them to ground through 10 kohm resistors or use them in the GPIF II waveform. Per Infineon FX3 hardware guidance, the external 24 MHz crystal must have <=50 ppm tolerance and load capacitance matched to the on-chip load for USB compliance.
Informations de conformité
RoHS compliant per Infineon product page. USB-IF certified under TID # 340800007. AEC-Q100 not applicable - choose CYUSB3035-BZXI for industrial temperature range.
