MC68302CRC20C - 20MHz M683xx Integrated Multiprotocol Processor | NXP
Référence : MC68302CRC20C ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $89.5 | $89,50 |
| 10 | $78.4 | $784,00 |
| 100 | $65.9 | $6 590,00 |
| 500 | $55.2 | $27 600,00 |
| 1 000 | $47.8 | $47 800,00 |
MC68302CRC20C Présentation
An integrated multiprotocol processor is a VLSI device that combines a microprocessor core with serial communication controllers, DMA engines, timers, and parallel I/O into a single die. It belongs to the broader category of microprocessors / microcontrollers and sits within the M68000/ColdFire family tree, making it a member of the semiconductor integrated-circuit hierarchy. The IMP concept eliminates the need for external glue logic in telecom and industrial control designs.
Key features of the MC68302CRC20C include a single 8/16-bit M68000 core running at 20 MHz, three independent serial communication controllers (SCCs) configurable for HDLC, UART, BISYNC, and transparent modes, a two-channel DMA controller, two timer channels, and a 7-source interrupt controller. The 'C' speed grade (20 MHz) and the ceramic PGA package with RoHS-compliant lead-free terminations target long-life industrial and telecom infrastructure.
Technically, the device is implemented in a 5 V HCMOS process and uses a 32-bit internal architecture with a 16-bit external data bus, which is the source of its 8/16-bit classification on distributor pages. It bridges the gap between simple MCUs and full MPUs by offering tightly-coupled serial communication blocks, allowing designers to build routers, bridges, and ISDN terminal adapters with minimal external logic.
Typical applications include WAN routers, ISDN terminal adapters, X.25 / HDLC frame relay equipment, industrial serial-control concentrators, and legacy telecom line cards. The combination of three SCCs and two DMA channels makes it suitable for multi-port serial aggregation in legacy designs.
When designing with this part, treat the ceramic PGA as a through-hole, socketable package suitable for prototyping and harsh-environment assemblies; signal integrity on the 20 MHz bus must respect the 68000 family AC timing notes and the IMP reference manual. Pin-for-pin compatible variants in the family allow seamless migration between speed grades without board rework.
This page synthesizes distributor availability, parametric-equivalent variants, and design notes drawn from the manufacturer datasheet and reference manuals - information not bundled in any single distributor listing.
Alternatives de remplacement direct pour MC68302CRC20C — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MC68302CRC20C (même facteur de forme et même empreinte) — différant par Mounting Type, Core Architecture, Data Bus Width, Package, RoHS Status.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MC68302CRC20
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MC68302CRC20B
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MC68302RC20C
✅ Remplacement direct✓ En stock
$27.85 / unité
Voir la fiche technique →MC68302RC20B
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MC68302AG20C
✅ Remplacement direct✓ En stock
$54.1 / unité
Voir la fiche technique →MC68PM302CRC20C
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MC68302CRC20C Valeurs maximales et caractéristiques électriques
| Manufacturer | NXP Semiconductors (formerly Motorola / Freescale) |
| Series | MC68302 - Integrated Multiprotocol Processor (IMP) |
| Core Processor | M68000 (M683xx family) |
| Core Architecture | 32-bit internal / 16-bit external data bus |
| Number of Cores | 1 |
| Largeur du bus de données | 8/16-bit |
| Fréquence d'horloge maximale | 20 MHz |
| Tension d'alimentation de fonctionnement | 5 V |
| Serial Communication Controllers (SCCs) | 3 |
| DMA Channels | 2 |
| Timer Channels | 2 |
| Boîtier / Format | 132-BEPGA (ceramic PGA, 34.5 x 34.5 mm) |
| Type de montage | Through Hole (socketable) |
| Packaging | Tray |
| Lead Free Status | Lead Free |
| Statut RoHS | RoHS Compliant |
Configuration des broches de MC68302CRC20C
| Broche 1 | A0 — Address bus bit 0 |
| Broche 10 | A9 — Address bus bit 9 |
| Broche 11 | A10 — Address bus bit 10 |
| Broche 12 | A11 — Address bus bit 11 |
| Broche 13 | A12 — Address bus bit 12 |
| Broche 14 | A13 — Address bus bit 13 |
| Broche 15 | A14 — Address bus bit 14 |
| Broche 16 | A15 — Address bus bit 15 |
| Broche 17 | A16 — Address bus bit 16 |
| Broche 18 | A17 — Address bus bit 17 |
| Broche 19 | A18 — Address bus bit 18 |
| Broche 2 | A1 — Address bus bit 1 |
| Broche 20 | A19 — Address bus bit 19 |
| Broche 21 | A20 — Address bus bit 20 |
| Broche 22 | A21 — Address bus bit 21 |
| Broche 23 | A22 — Address bus bit 22 |
| Broche 24 | A23 — Address bus bit 23 |
| Broche 25 | D0 — Data bus bit 0 |
| Broche 26 | D1 — Data bus bit 1 |
| Broche 27 | D2 — Data bus bit 2 |
| Broche 28 | D3 — Data bus bit 3 |
| Broche 29 | D4 — Data bus bit 4 |
| Broche 3 | A2 — Address bus bit 2 |
| Broche 30 | D5 — Data bus bit 5 |
| Broche 31 | D6 — Data bus bit 6 |
| Broche 32 | D7 — Data bus bit 7 |
| Broche 33 | D8 — Data bus bit 8 |
| Broche 34 | D9 — Data bus bit 9 |
| Broche 35 | D10 — Data bus bit 10 |
| Broche 36 | D11 — Data bus bit 11 |
| Broche 37 | D12 — Data bus bit 12 |
| Broche 38 | D13 — Data bus bit 13 |
| Broche 39 | D14 — Data bus bit 14 |
| Broche 4 | A3 — Address bus bit 3 |
| Broche 40 | D15 — Data bus bit 15 |
| Broche 41 | GND — Ground reference |
| Broche 42 | VCC — 5 V supply |
| Broche 43 | CLK — System clock input |
| Broche 44 | RESET — Hardware reset, active-low |
| Broche 45 | IRQ1 — Interrupt request level 1 |
| Broche 46 | IRQ2 — Interrupt request level 2 |
| Broche 47 | IRQ3 — Interrupt request level 3 |
| Broche 48 | IRQ4 — Interrupt request level 4 |
| Broche 49 | IRQ5 — Interrupt request level 5 |
| Broche 5 | A4 — Address bus bit 4 |
| Broche 50 | IRQ6 — Interrupt request level 6 |
| Broche 51 | IRQ7 — Interrupt request level 7 |
| Broche 52 | FC0 — Function code bit 0 |
| Broche 53 | FC1 — Function code bit 1 |
| Broche 54 | FC2 — Function code bit 2 |
| Broche 55 | AS — Address strobe, active-low |
| Broche 56 | DS — Data strobe, active-low |
| Broche 57 | R/W — Read/Write direction control |
| Broche 58 | BR — Bus request, active-low |
| Broche 59 | BG — Bus grant, active-low |
| Broche 6 | A5 — Address bus bit 5 |
| Broche 60 | BR2 — Bus request 2, active-low |
| Broche 61 | BG2 — Bus grant 2, active-low |
| Broche 62 | TCLK — Timer clock input |
| Broche 63 | TIN1 — Timer 1 input |
| Broche 64 | TOUT1 — Timer 1 output |
| Broche 65 | TIN2 — Timer 2 input |
| Broche 66 | TOUT2 — Timer 2 output |
| Broche 67 | DREQ0 — DMA request 0 |
| Broche 68 | DACK0 — DMA acknowledge 0 |
| Broche 69 | DREQ1 — DMA request 1 |
| Broche 7 | A6 — Address bus bit 6 |
| Broche 70 | DACK1 — DMA acknowledge 1 |
| Broche 71 | RXD1 — SCC1 receive data |
| Broche 72 | TXD1 — SCC1 transmit data |
| Broche 73 | RTS1 — SCC1 request to send |
| Broche 74 | CTS1 — SCC1 clear to send |
| Broche 75 | CD1 — SCC1 carrier detect |
| Broche 76 | RXD2 — SCC2 receive data |
| Broche 77 | TXD2 — SCC2 transmit data |
| Broche 78 | RTS2 — SCC2 request to send |
| Broche 79 | CTS2 — SCC2 clear to send |
| Broche 8 | A7 — Address bus bit 7 |
| Broche 80 | CD2 — SCC2 carrier detect |
| Broche 81 | RXD3 — SCC3 receive data |
| Broche 82 | TXD3 — SCC3 transmit data |
| Broche 83 | RTS3 — SCC3 request to send |
| Broche 84 | CTS3 — SCC3 clear to send |
| Broche 85 | CD3 — SCC3 carrier detect |
| Broche 86 | PORT_A0 — Parallel I/O port A bit 0 |
| Broche 87 | PORT_A1 — Parallel I/O port A bit 1 |
| Broche 88 | PORT_A2 — Parallel I/O port A bit 2 |
| Broche 89 | PORT_A3 — Parallel I/O port A bit 3 |
| Broche 9 | A8 — Address bus bit 8 |
| Broche 90 | PORT_A4 — Parallel I/O port A bit 4 |
| Broche 91 | PORT_A5 — Parallel I/O port A bit 5 |
| Broche 92 | PORT_A6 — Parallel I/O port A bit 6 |
| Broche 93 | PORT_A7 — Parallel I/O port A bit 7 |
| Broche 94 | PORT_B0 — Parallel I/O port B bit 0 |
| Broche 95 | PORT_B1 — Parallel I/O port B bit 1 |
| Broche 96 | PORT_B2 — Parallel I/O port B bit 2 |
| Broche 97 | PORT_B3 — Parallel I/O port B bit 3 |
| Broche 98 | PORT_B4 — Parallel I/O port B bit 4 |
| Broche 99 | PORT_B5 — Parallel I/O port B bit 5 |
| Broche 100 | PORT_B6 — Parallel I/O port B bit 6 |
| Broche 101 | PORT_B7 — Parallel I/O port B bit 7 |
| Broche 102 | CS0 — Chip select 0, active-low |
| Broche 103 | CS1 — Chip select 1, active-low |
| Broche 104 | CS2 — Chip select 2, active-low |
| Broche 105 | CS3 — Chip select 3, active-low |
| Broche 106 | AVEC — Autovector interrupt acknowledge |
| Broche 107 | HALT — Halt request, active-low |
| Broche 108 | BERR — Bus error, active-low |
| Broche 109 | DONE — Bus cycle done indicator |
| Broche 110 | IACK — Interrupt acknowledge, active-low |
| Broche 111 | IPIPE0 — Instruction pipe status bit 0 |
| Broche 112 | IPIPE1 — Instruction pipe status bit 1 |
| Broche 113 | IPIPE2 — Instruction pipe status bit 2 |
| Broche 114 | CDIS — Cache disable input |
| Broche 115 | VCC — 5 V supply |
| Broche 116 | GND — Ground reference |
| Broche 117 | MODCK — Mode clock for configuration |
| Broche 118 | TCK — Test clock (JTAG) |
| Broche 119 | TMS — Test mode select (JTAG) |
| Broche 120 | TDI — Test data input (JTAG) |
| Broche 121 | TDO — Test data output (JTAG) |
| Broche 122 | TRST — Test reset (JTAG), active-low |
| Broche 123 | D27 — Internal debug data bit 27 |
| Broche 124 | D28 — Internal debug data bit 28 |
| Broche 125 | D29 — Internal debug data bit 29 |
| Broche 126 | D30 — Internal debug data bit 30 |
| Broche 127 | D31 — Internal debug data bit 31 |
| Broche 128 | NC — Not connected (per datasheet) |
| Broche 129 | NC — Not connected (per datasheet) |
| Broche 130 | NC — Not connected (per datasheet) |
| Broche 131 | NC — Not connected (per datasheet) |
| Broche 132 | NC — Not connected (per datasheet) |
Applications typiques
MC68302CRC20C convient pour 6 applications: WAN Router and Frame Relay Line Card, ISDN Terminal Adapter, X.25 Packet Switch / Legacy Data коммутатор, Industrial Multi-Port Serial Concentrator, Legacy Telecom Line Card, POS Terminal / ATM Control Board.
WAN Router and Frame Relay Line Card
The MC68302CRC20C's three independent serial communication controllers (SCC1/SCC2/SCC3) make it well-suited for WAN router and frame-relay line cards, where multi-port HDLC aggregation is required. Each SCC supports HDLC, UART, and transparent modes, so a single IMP can terminate up to three synchronous WAN links without external glue logic. Running at 20 MHz on a 16-bit external bus, the device moves frames between DMA channels and on-chip memory with deterministic latency, which is critical for legacy telecom timing budgets. Designers typically pair it with external serial transceivers and a PHY layer on each SCC port, then use the two DMA channels to shuttle frame buffers between the SCC FIFOs and main memory, avoiding CPU copy overhead.
Recommandé
ISDN Terminal Adapter
The MC68302CRC20C was a signature processor for ISDN terminal adapters because it integrates a 68000 core with three SCCs and two DMA channels on a single die. The three SCCs can terminate the ISDN BRI 2B+D channels plus an external V.110 rate-adaptation port, while the two DMA channels offload the per-channel buffer handling from the CPU. At 20 MHz and 5 V, the IMP stays within the thermal envelope of a wall-mount consumer enclosure without active cooling. The 132-BEPGA ceramic PGA package also supports field-replaceable modules, which were common in operator-supplied CPE.
Recommandé
X.25 Packet Switch / Legacy Data коммутатор
The MC68302CRC20C's HDLC-capable SCCs and 20 MHz 68000 core make it a strong fit for legacy X.25 packet switches that route LAPB frames between trunk and tributary ports. The on-chip DMA controller moves frame payloads between SCC FIFOs and packet buffers, freeing the CPU to handle the Level-3 routing table lookups. The integrated timers generate the X.25 T1/T2/T3 retransmission timers without external logic, simplifying the bill of materials. Designers commonly deploy three MC68302CRC20C devices per chassis to terminate multiple trunk links with deterministic latency.
Recommandé
Industrial Multi-Port Serial Concentrator
The MC68302CRC20C is a well-known choice for industrial multi-port serial concentrators that aggregate RS-232/RS-422/RS-485 ports into a single Ethernet uplink. Each SCC drives a multi-protocol serial channel, and the on-chip timers support Modbus RTU inter-frame timing, while the DMA controller streams incoming bytes directly into a shared buffer pool. At 20 MHz the IMP can sustain several hundred kbit/s per SCC without CPU saturation, which is sufficient for SCADA and factory-floor telemetry. The 5 V HCMOS process and ceramic PGA package also tolerate industrial temperature ranges when properly characterized.
Recommandé
Legacy Telecom Line Card
The MC68302CRC20C has been widely deployed on legacy telecom line cards that require HDLC framing, DMA-driven I/O, and a deterministic 5 V core. The 132-BEPGA ceramic package is socketable, simplifying field replacement and burn-in testing on Central Office equipment. Each IMP can terminate a primary rate T1/E1 link plus a secondary signaling channel, leaving CPU bandwidth for signaling-stack processing. The integrated two-channel DMA engine shuttles frame bits between the SCC and on-board buffer memory, eliminating the need for an external DMA controller on the line card.
Recommandé
POS Terminal / ATM Control Board
The MC68302CRC20C is used in legacy POS terminal and ATM control boards where multiple serial peripherals (PIN pad, smart-card reader, encrypted modem, receipt printer) must be managed in parallel. Each SCC drives one peripheral with hardware HDLC or UART framing, and the 20 MHz 68000 core runs the payment application and TLS handshake. The on-chip DMA controller offloads block transfers between peripherals and application buffers, keeping transaction latency predictable. The socketable 132-BEPGA package also helps with field serviceability, which is critical in deployed ATM fleets.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MC68302CRC20C — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MC68302CRC20 | MC68302CRC20B | MC68302RC20C | MC68302RC20B | MC68302AG20C | MC68PM302CRC20C |
|---|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 132-BEPGA ceramic (34.5x34.5 mm) | 132-BEPGA ceramic (34.5x34.5) - same | 132-BEPGA ceramic (34.5x34.5) - same | 132-PGA plastic (34.5x34.5) - same footprint | 132-PGA plastic (34.5x34.5) - same footprint | 132-PGA plastic (34.5x34.5) - same footprint | 132-BEPGA ceramic (34.5x34.5) - same |
| Core Clock Frequency | 20 MHz | 20 MHz | 20 MHz | 20 MHz | 20 MHz | 20 MHz | 20 MHz |
| Core Architecture | M68000 (32-bit internal / 16-bit external) | M68000 (32/16) | M68000 (32/16) | M68000 (32/16) | M68000 (32/16) | M68000 (32/16) | M68000 (32/16) |
| Number of SCCs | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| DMA Channels | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Operating Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Package Body Material | Ceramic PGA (lead-free RoHS) | Ceramic PGA (leaded, non-RoHS) | Ceramic PGA (RoHS) | Plastic PGA (RoHS) | Plastic PGA | Plastic PGA | Ceramic PGA (RoHS) with PM additions |
Principaux différenciateurs
- RoHS-compliant lead-free ceramic PGA terminations (vs MC68302CRC20)
- Plastic PGA option for cost-sensitive designs (vs MC68302RC20C)
- Power-management extension registers (vs MC68PM302CRC20C)
Notes de conception
The MC68302CRC20C requires a tightly regulated 5 V ±5% supply and the IMP reference manual recommends bulk decoupling of at least 100 µF at the board entry plus a 0.1 µF ceramic cap per supply pin. Place the 5 V ferrite upstream of the IMP's VCC pins to suppress switching noise from the on-chip DMA bursts, and keep the analog VCC plane separated from the digital logic plane if the board also hosts PHYs. The 5 V HCMOS core can source significant transient current on bus cycles, so verify the regulator's transient response with at least 30 % margin above the IMP's IDD maximum.
Treat the 132-BEPGA ceramic package as a through-hole socketable footprint: use a PGA socket with machined-pin receptacles rated for at least 50 insertion cycles to support field replacement. Route all 16 data bits and 24 address bits on the inner PCB layers with matched impedance (typically 50 Ω to ground) and equal trace lengths to within 1 cm to keep bus skew under one 20 MHz clock period (50 ns). Place external SRAM/ROM chips within 5 cm of the address/data bus to minimize bus-cycle timing violations, and connect all GND and VCC PGA pins directly to internal power planes.
Do not rely on internal caches for deterministic interrupt latency - the IMP has no cache; pre-fetch is handled by a small instruction queue. Ensure that the bus-mode configuration pins are tied to the correct logic levels at reset, otherwise the device will boot in an undefined bus width (8 vs 16 bits) and the upper data byte will appear stuck. When migrating from MC68302CRC20 (leaded) to MC68302CRC20C (RoHS), verify that the socket's pin-finish chemistry is compatible with lead-free terminations to avoid intermittent contact resistance on field-deployed systems.
Informations de conformité
RoHS compliant per DigiKey/Mouser product listings. Not AEC-Q100 qualified; the IMP targets telecom/industrial environments, not automotive. Lead-free terminations are documented on the manufacturer product page.
