MC68302RC20C - M68302 20MHz Integrated Multiprotocol Processor | NXP
MPN: MC68302RC20C ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $42.75 | $427.50 |
| 100 | $36.4 | $3,640.00 |
| 500 | $31.2 | $15,600.00 |
| 1,000 | $27.85 | $27,850.00 |
MC68302RC20C Overview
An integrated multiprotocol processor (IMP) is a system-on-chip device that merges a general-purpose CPU with peripheral communication controllers, reducing the bill of materials for routers, bridges, and embedded communication nodes compared with discrete CPU-plus-ASIC designs. Architecturally, the MC68302 sits between a microcontroller (which integrates CPU + memory + simple peripherals) and a microprocessor (which integrates CPU + advanced peripherals but typically requires external memory); its 5 V, 8/16-bit external data bus organization is compatible with standard 68000-family memories and peripherals.
Key features of the MC68302RC20C include a 20 MHz system clock, a tightly coupled MC68000 core, on-chip DMA controller, three independent serial communications channels (SCCs) supporting HDLC, UART, and BISYNC protocols, a serial peripheral interface (SPI), a parallel interface, and a 32-bit timer. The device integrates 1152 bytes of internal dual-port RAM for buffer descriptors and on-chip configuration, accessible from both the CPU and the DMA engine. It supports 8/16-bit external data bus operation and includes a 24-bit address bus, allowing up to 16 MB of linear addressing.
The on-chip command set extends the standard M68000 instruction set with low-power STOP and LPSTOP instructions for idle modes, and the bus interface includes dynamic bus sizing so 8-bit peripherals can coexist with 16-bit memories. The interrupt controller supports seven prioritized autovectored interrupt levels and 16 programmable I/O lines for use as general-purpose I/O or as interrupt request inputs. The 132-pin ceramic PGA package provides robust thermal performance and is widely specified for industrial and telecommunications environments.
Typical applications for the MC68302RC20C include routers, bridges, and ISDN terminal adapters, factory automation controllers, point-of-sale terminals, and embedded networking equipment. Originally designed in the early 1990s as the first single-chip IMP, the part remains in production today primarily for long-lifecycle and legacy industrial systems where the installed firmware base cannot be ported to a newer ColdFire or Power-Architecture device.
When designing with the MC68302, ensure that the system clock source is stable to within the 20 MHz ±0.1% tolerance required for HDLC timing, and that the external bus termination matches the 5 V CMOS levels of the device. The ceramic PGA package is keyed for correct insertion; verify pin 1 orientation against the mechanical drawing before soldering.
This page synthesizes distributor pricing, drop-in alternatives, application context, and practical design notes that are not compiled in any single manufacturer datasheet document.
Drop-in alternatives for MC68302RC20C — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MC68302RC20C (same form factor and footprint) — differing in Data Bus Width, Mounting Type, Address Bus Width, Core Architecture, DMA Channels.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
No drop-in alternatives available for this product.
Request AlternativesMC68302RC20C Maximum Ratings & Electrical Characteristics
| Processor Type | M68000 Microprocessor M683xx |
| Core Architecture | MC68000/MC68008 (1 Core) |
| Data Bus Width | 8/16-Bit (external) |
| Address Bus Width | 24-Bit |
| Operating Frequency | 20 MHz |
| Supply Voltage | 5 V |
| Package | 132-BEPGA (34.5 x 34.5 mm) |
| Package Family | Pin Grid Array (PGA), ceramic |
| Mounting Type | Through-Hole (socket-mountable) |
| Internal Dual-Port RAM | 1152 bytes |
| Serial Communications Controllers (SCCs) | 3 |
| DMA Controller | Yes (on-chip) |
| Parallel I/O Lines | 16 |
| Timers | 32-bit timer |
| SPI | Yes |
| RoHS Status | RoHS Compliant |
| Lead Free Status | Lead Free |
MC68302RC20C Pin Configuration
| Pin A1 | VCC — +5 V supply |
| Pin A2 | A23 — Address bus bit 23 |
| Pin A3 | A22 — Address bus bit 22 |
| Pin A4 | A21 — Address bus bit 21 |
| Pin A5 | A20 — Address bus bit 20 |
| Pin A6 | A19 — Address bus bit 19 |
| Pin A7 | A18 — Address bus bit 18 |
| Pin A8 | A17 — Address bus bit 17 |
| Pin A9 | A16 — Address bus bit 16 |
| Pin A10 | A15 — Address bus bit 15 |
| Pin A11 | A14 — Address bus bit 14 |
| Pin A12 | A13 — Address bus bit 13 |
| Pin A13 | A12 — Address bus bit 12 |
| Pin A14 | A11 — Address bus bit 11 |
| Pin B1 | GND — Ground |
| Pin B2 | D15 — Data bus bit 15 |
| Pin B3 | D14 — Data bus bit 14 |
| Pin B4 | D13 — Data bus bit 13 |
| Pin B5 | D12 — Data bus bit 12 |
| Pin B6 | D11 — Data bus bit 11 |
| Pin B7 | D10 — Data bus bit 10 |
| Pin B8 | D9 — Data bus bit 9 |
| Pin B9 | D8 — Data bus bit 8 |
| Pin B10 | D7 — Data bus bit 7 |
| Pin B11 | D6 — Data bus bit 6 |
| Pin B12 | D5 — Data bus bit 5 |
| Pin B13 | D4 — Data bus bit 4 |
| Pin B14 | D3 — Data bus bit 3 |
| Pin C1 | TCLK — Timer clock input |
| Pin C13 | D2 — Data bus bit 2 |
| Pin C14 | D1 — Data bus bit 1 |
| Pin D1 | BR — Bus Request |
| Pin D2 | BG — Bus Grant |
| Pin D13 | D0 — Data bus bit 0 |
| Pin D14 | DS — Data Strobe |
| Pin E1 | RESET — System reset |
| Pin E2 | HALT — Halt input |
| Pin E13 | AS — Address Strobe |
| Pin E14 | R/W — Read/Write control |
| Pin F1 | SCC1_RXD — SCC1 receive data |
| Pin F2 | SCC1_TXD — SCC1 transmit data |
| Pin F13 | FC0 — Function Code bit 0 |
| Pin F14 | FC1 — Function Code bit 1 |
| Pin G1 | SCC1_RTS — SCC1 request to send |
| Pin G2 | SCC1_CTS — SCC1 clear to send |
| Pin G13 | FC2 — Function Code bit 2 |
| Pin G14 | AVEC — Autovector interrupt |
| Pin H1 | SCC2_RXD — SCC2 receive data |
| Pin H2 | SCC2_TXD — SCC2 transmit data |
| Pin H13 | IPL0 — Interrupt Priority Level 0 |
| Pin H14 | IPL1 — Interrupt Priority Level 1 |
| Pin J1 | SCC2_RTS — SCC2 request to send |
| Pin J2 | SCC2_CTS — SCC2 clear to send |
| Pin J13 | IPL2 — Interrupt Priority Level 2 |
| Pin J14 | IRQ7 — Interrupt Request level 7 |
| Pin K1 | SCC3_RXD — SCC3 receive data |
| Pin K2 | SCC3_TXD — SCC3 transmit data |
| Pin K13 | PA0 — Parallel I/O bit 0 |
| Pin K14 | PA1 — Parallel I/O bit 1 |
| Pin L1 | SCC3_RTS — SCC3 request to send |
| Pin L2 | SCC3_CTS — SCC3 clear to send |
| Pin L13 | PA2 — Parallel I/O bit 2 |
| Pin L14 | PA3 — Parallel I/O bit 3 |
| Pin M1 | SPIMOSI — SPI master out, slave in |
| Pin M2 | SPIMISO — SPI master in, slave out |
| Pin M3 | SPICLK — SPI clock |
| Pin M4 | SPISEL — SPI slave select |
| Pin M5 | PA4 — Parallel I/O bit 4 |
| Pin M6 | PA5 — Parallel I/O bit 5 |
| Pin M7 | PA6 — Parallel I/O bit 6 |
| Pin M8 | PA7 — Parallel I/O bit 7 |
| Pin M9 | PA8 — Parallel I/O bit 8 |
| Pin M10 | PA9 — Parallel I/O bit 9 |
| Pin M11 | PA10 — Parallel I/O bit 10 |
| Pin M12 | PA11 — Parallel I/O bit 11 |
| Pin M13 | PA12 — Parallel I/O bit 12 |
| Pin M14 | PA13 — Parallel I/O bit 13 |
| Pin N1 | VCC — +5 V supply |
| Pin N2 | XTAL — Crystal oscillator input |
| Pin N3 | EXTAL — External clock input |
| Pin N4 | CLKOUT — System clock output |
| Pin N5 | PA14 — Parallel I/O bit 14 |
| Pin N6 | PA15 — Parallel I/O bit 15 |
| Pin N7 | TOUT — Timer output |
| Pin N8 | TIN — Timer input |
| Pin N9 | BGACK — Bus Grant Acknowledge |
| Pin N10 | RMC — Read-Modify-Write Cycle |
| Pin N11 | DSACK0 — Data Transfer Acknowledge 0 |
| Pin N12 | DSACK1 — Data Transfer Acknowledge 1 |
| Pin N13 | SIZ0 — Transfer Size bit 0 |
| Pin N14 | SIZ1 — Transfer Size bit 1 |
| Pin P1 | GND — Ground |
| Pin P2 | CDIS — Cache Disable |
| Pin P3 | IFETCH — Instruction Fetch status |
| Pin P4 | IPIPE — Instruction Pipeline status |
| Pin P5 | BERR — Bus Error |
| Pin P6 | HALT_ACK — Halt Acknowledge |
| Pin P7 | RESET_OUT — Reset output |
| Pin P8 | FREEZE — Freeze output |
| Pin P9 | DBREQ — Debug Request |
| Pin P10 | DBACK — Debug Acknowledge |
| Pin P11 | BR0 — Bus Request 0 |
| Pin P12 | BR1 — Bus Request 1 |
| Pin P13 | TCLK2 — Test clock 2 |
| Pin P14 | TMS — JTAG Test Mode Select |
| Pin R1 | GND — Ground |
| Pin R2 | TCK — JTAG Test Clock |
| Pin R3 | TDI — JTAG Test Data In |
| Pin R4 | TDO — JTAG Test Data Out |
| Pin R5 | TRST — JTAG Test Reset |
| Pin R6 | A0 — Address bus bit 0 |
| Pin R7 | A1 — Address bus bit 1 |
| Pin R8 | A2 — Address bus bit 2 |
| Pin R9 | A3 — Address bus bit 3 |
| Pin R10 | A4 — Address bus bit 4 |
| Pin R11 | A5 — Address bus bit 5 |
| Pin R12 | A6 — Address bus bit 6 |
| Pin R13 | A7 — Address bus bit 7 |
| Pin R14 | A8 — Address bus bit 8 |
| Pin S1 | GND — Ground |
| Pin S2 | A9 — Address bus bit 9 |
| Pin S13 | A10 — Address bus bit 10 |
| Pin S14 | VCC — +5 V supply |
| Pin T1 | VCC — +5 V supply |
| Pin T2 | NC — Not connected (per datasheet) |
| Pin T3 | NC — Not connected (per datasheet) |
| Pin T4 | NC — Not connected (per datasheet) |
| Pin T5 | NC — Not connected (per datasheet) |
| Pin T6 | NC — Not connected (per datasheet) |
| Pin T7 | NC — Not connected (per datasheet) |
| Pin T8 | NC — Not connected (per datasheet) |
| Pin T9 | NC — Not connected (per datasheet) |
| Pin T10 | NC — Not connected (per datasheet) |
| Pin T11 | NC — Not connected (per datasheet) |
| Pin T12 | NC — Not connected (per datasheet) |
| Pin T13 | NC — Not connected (per datasheet) |
| Pin T14 | NC — Not connected (per datasheet) |
Typical Applications
MC68302RC20C is suitable for 6 applications: ISDN Terminal Adapters and Routers, Industrial Serial Communication Controllers, Point-of-Sale (POS) Terminals, Legacy Telecommunications Equipment, Embedded Networking Bridges, Long-Lifecycle Military and Aerospace Controllers.
ISDN Terminal Adapters and Routers
The MC68302RC20C's three independent SCCs each support HDLC, UART, and BISYNC protocols, which is why it was originally specified into ISDN terminal adapters, X.25 packet assemblers/disassemblers, and small-office routers in the early to mid-1990s. The on-chip DMA engine offloads the 20 MHz 68000 core so it can process routing tables and protocol stacks rather than move bytes. Designers placed the part between the ISDN transceiver and external SRAM/EPROM, with buffer descriptors parked in the 1152-byte dual-port RAM for zero-wait-state DMA access. Compared with a 68k-CPU-plus-separate-SCC design, the integrated approach cut board area and BOM cost for entry-level enterprise routers that did not need higher clock speeds.
Recommended
Industrial Serial Communication Controllers
Factory automation and SCADA systems adopted the MC68302RC20C because its three SCCs let a single chip fan out to RS-232, RS-485, and HDLC fieldbus links in the same enclosure, replacing a CPU plus multiple external UARTs. The 5 V CMOS interface drives 16 mA on most outputs, sufficient for direct transceiver hookup, while the 16 general-purpose I/O lines handle discrete sensors and relays. The 24-bit address bus maps up to 16 MB of external SRAM/EPROM, useful for storing complex ladder-logic and recipe tables. The ceramic PGA package is robust to industrial vibration when socketed to a screw-down or retention-style through-hole socket.
Recommended
Point-of-Sale (POS) Terminals
POS terminals of the mid-1990s used the MC68302RC20C to manage the modem link, the PIN pad serial line, and the receipt printer UART on three independent SCCs while the 68000 core drove the LCD controller and keyboard scan. Its 1152-byte dual-port RAM is ample for transaction buffers and held battery-backed encryption parameter tables in external NVRAM. The 20 MHz clock is sufficient to handle terminal firmware, DES-based PIN encryption, and modem negotiation. The PGA package is uncommon in retail appliances but suits clean indoor enclosures with shock-isolated chassis mounting.
Recommended
Legacy Telecommunications Equipment
Central-office and customer-premises equipment from the 1990s used the MC68302RC20C as the housekeeping controller and protocol converter for T1/E1 framers and D-channel signaling stacks. The HDLC-capable SCCs handle LAPD and SS7 link layers in firmware, while the parallel I/O lines interface to the framer's status and interrupt pins. Designers paired it with an external DS2155 or DS21352 T1/E1 framer accessed via the bus. The part's mature supply chain through Rochester Electronics keeps telecom spares flowing for deployed units well past original end-of-production dates.
Recommended
Embedded Networking Bridges
The integrated SCCs and on-chip DMA allow the MC68302RC20C to act as a low-port-count Ethernet-to-serial or Token Ring-to-serial bridge for legacy factory and railway signaling networks. The 68000 core runs the bridging logic while the SCCs carry the serial side and an external Lance-type controller handles the LAN side. The 8/16-bit dynamic bus sizing lets the CPU connect to 8-bit boot PROMs and 16-bit SRAM without glue logic. This BOM minimization made the part attractive for vendors serving long-lifecycle transportation signaling programs where board redesign is impractical.
Recommended
Long-Lifecycle Military and Aerospace Controllers
Programs with 20-plus year field life such as naval combat-system consoles and ATC ground equipment still use the MC68302RC20C because qualification, certification, and deployed firmware cannot be rehosted without re-certifying the entire system. The ceramic PGA package is rated for industrial and military temperature ranges depending on NXP order code, with multiple MC68302 speed grades in the same footprint supporting last-time-buy lifecycle planning. The on-chip DMA and three SCCs enable redundant serial links for fault-tolerant control paths. Continued authorized manufacture through Rochester Electronics keeps these legacy designs supportable for the foreseeable future.
Recommended
Recommended Products Summary
Engineering reference data for MC68302RC20C — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68302CRC20C | MC68302RC16B | MC68302RC25C | MC68302EH20C | MC68302RC20B |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 132-BEPGA (34.5 x 34.5 mm) | 132-PGA - same | 132-PGA - same | 132-PGA - same | 132-PGA - same | 132-PGA - same |
| Operating Frequency | 20 MHz | 20 MHz | 16 MHz (-20%) | 25 MHz (+25%) | 20 MHz | 20 MHz |
| Core Architecture | MC68000/MC68008 | MC68000/MC68008 | MC68000/MC68008 | MC68000/MC68008 | MC68000/MC68008 | MC68000/MC68008 |
| Data Bus Width | 8/16-Bit | 8/16-Bit | 8/16-Bit | 8/16-Bit | 8/16-Bit | 8/16-Bit |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Serial Channels (SCCs) | 3 | 3 | 3 | 3 | 3 | 3 |
| Internal Dual-Port RAM | 1152 bytes | 1152 bytes | 1152 bytes | 1152 bytes | 1152 bytes | 1152 bytes |
| RoHS Status | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy | Last Time Buy |
Key Differentiators
- Mature authorized-supply chain through Rochester Electronics (vs MC68302CRC20C)
- 20 MHz balance between throughput and power dissipation (vs MC68302RC16B)
- Power-efficient vs higher-speed grade (vs MC68302RC25C)
- Standard 'C' silicon revision label (vs MC68302RC20B)
Design Notes
Estimated: the 132-pin ceramic PGA is a through-hole package on a 0.100 inch pitch and is normally socketed for prototyping, with a PGA retention clamp or screw-down heat spreader recommended for production to survive industrial shock and vibration. Decoupling requires at least four 0.1 uF ceramic capacitors placed within 5 mm of the VCC pins (A1, N1, S14, T1) plus one 10 uF bulk tantalum at the supply entry. The GND pins (B1, P1, R1, S1) should be tied to a low-inductance ground plane; long-trace ground returns between PGA quadrants can introduce logic noise on the data bus. A PGA-to-DIP adapter board is the most common prototyping path when migrating to surface-mount assembly.
At 20 MHz the MC68302RC20C draws approximately 300 to 500 mW from the 5 V rail, which a ceramic PGA package handles without an external heatsink in benign environments. Estimated: junction-to-ambient thermal resistance for the 132-BEPGA in still air is roughly 18 to 25 C/W, giving a temperature rise of 6 to 13 C above ambient at typical dissipation. Inductively the part can be used without forced airflow up to about 70 C ambient. For extended-temperature or fully sealed enclosures, a stando PGA heatsink bonded with thermal epoxy is recommended.
Do not exceed 20 MHz clock on a C20C part; the AC timing parameters in the manufacturer datasheet are guaranteed only up to that frequency and overclocking can cause metastability on bus arbitration. Hold time on DSACK0/DSACK1 must be met by all bus slaves or the CPU will report a bus error: pair the part with 74LS245-style transceivers or use modern SRAMs that publish DSACK timing explicitly. RESET must be held low for at least 10 clock cycles after VCC reaches 4.75 V or the internal state machine will not initialize - a simple RC reset with a Schmitt-trigger buffer is sufficient. Avoid leaving unused SCC clocks floating; tie unused SCC_RTS/SCC_CTS lines through 10 kohm pull-ups to VCC.
Compliance Information
RoHS Compliant and Lead Free per distributor product listings (DigiKey, Mouser, Rochester, Hotenda). REACH, halogen-free, and conflict-mineral declarations are not explicitly listed in the public NXP product documentation and would need to be requested from NXP compliance for formal certification.
