MK21FN1M0VLQ12 - 120MHz Cortex-M4 MCU, 1MB Flash | NXP
Référence : MK21FN1M0VLQ12 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $15.34 | $15,34 |
| 10 | $13.81 | $138,10 |
| 100 | $12.27 | $1 227,00 |
| 500 | $10.74 | $5 370,00 |
| 1 000 | $9.2 | $9 200,00 |
MK21FN1M0VLQ12 Présentation
What is a microcontroller? A microcontroller is a single-chip computer that integrates a CPU core, program memory (Flash), data memory (SRAM), and peripheral interfaces into one package. Microcontrollers (MCUs) -> ARM Cortex-M microcontrollers -> Cortex-M4 with FPU -> Kinetis K series -> K21F sub-family. The K21F targets cost-sensitive, low-power, secure-connected applications and is positioned between the K10 (entry) and K60 (USB+Ethernet+high-speed) families within NXP's Kinetis portfolio.
Key features include a Cortex-M4 core with single-precision FPU and DSP instructions, 1MB Flash for application code, 128KB SRAM for data/buffers, Full-Speed USB 2.0 device/host/OTG with on-chip transceiver, hardware AES-128 encryption, secure anti-tamper pins, a 16-bit SAR ADC with up to 24 channels, two 12-bit DACs, and a low-power segment-LCD controller option. The 144-LQFP package exposes all major peripherals for maximum design flexibility.
The MK21FN1M0VLQ12 uses a Cortex-M4 core delivering 1.25 Dhrystone MIPS per MHz, with single-cycle MAC and hardware FPU for DSP workloads. The integrated power management supports multiple low-power modes (Wait, Stop, VLPR, VLPS) and an internal voltage regulator. The 1MB Flash is organized in a dual-bank arrangement for in-application programming and EEPROM emulation. Hardware AES-128 and tamper detection modules protect against software and physical attacks on connected endpoints.
Typical applications include USB-connected industrial control systems, secure point-of-sale (POS) terminals, anti-tamper smart meters, low-power human-machine interfaces (HMI) with segment LCD, consumer medical devices, and home/building automation gateways. The combination of Full-Speed USB, hardware crypto, and low-power Run/Stop modes makes the part especially suited to battery-powered secure peripherals.
When designing with the MK21FN1M0VLQ12, carefully review the decoupling network: place 100nF X7R capacitors as close as possible to every VDD/VSS pair, with bulk 4.7uF X5R near the regulator output. For USB, the D+/D- traces must be 90 ohm differential with no stubs; route over a continuous ground plane. Use the tamper pins to short/lock memory on intrusion, and select the boot mode via the security/boot configuration pins.
This page synthesizes distributor pricing, K21/K22/K24 drop-in and migration alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers select the right Kinetis K2x variant for their USB-connected secure design.
Alternatives de remplacement direct pour MK21FN1M0VLQ12 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MK21FN1M0VLQ12 (même facteur de forme et même empreinte) — différant par Package, Mounting Type, ADC, Maximum Clock Frequency, Core.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MK21FN1M0VLQ12R
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MK22FN1M0AVLQ12
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MK24FN1M0VLQ12
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MK22FN1M0VLQ12
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MK24FN1M0VLQ12R
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
MK21FN1M0VLQ12 Valeurs maximales et caractéristiques électriques
| Core | ARM Cortex-M4 with FPU and DSP |
| Bit Width | 32-bit |
| Fréquence d'horloge maximale | 120 MHz |
| Program Memory (Flash) | 1 MB (1M x 8) |
| RAM Size | 128 KB |
| Boîtier | 144-LQFP (20x20 mm) |
| Tension d'alimentation | 1.71 V to 3.6 V |
| USB Interface | USB 2.0 Full-Speed device/host/OTG with on-chip PHY |
| Hardware Encryption | AES-128 |
| Anti-Tamper Pins | Yes (secure tamper detection) |
| ADC | 16-bit SAR, multi-channel |
| DAC | 12-bit |
| Température de fonctionnement | -40 C to +105 C (V) |
| Type de montage | Surface Mount (LQFP) |
| Statut RoHS | Compliant |
| Lead Free | Yes |
| Lifecycle | NRND (Not Recommended for New Designs) |
Configuration des broches de MK21FN1M0VLQ12
| Broche 1 | PTB0 — GPIO / ADC0_SE0 / FTM0_CH0 |
| Broche 2 | PTB1 — GPIO / ADC0_SE1 / FTM0_CH1 |
| Broche 3 | PTB2 — GPIO / ADC0_SE2 / FTM0_CH2 |
| Broche 4 | PTB3 — GPIO / ADC0_SE3 / FTM0_CH3 |
| Broche 5 | VDD — Digital supply voltage |
| Broche 6 | VSS — Digital ground |
| Broche 7 | PTA0 — JTAG_TCLK / SWD_CLK |
| Broche 8 | PTA1 — JTAG_TDI / SWD_DIO |
| Broche 9 | PTA2 — JTAG_TDO / SWO |
| Broche 10 | PTA3 — JTAG_TMS / SWD_DIO |
| Broche 11 | PTA4 — JTAG_TRSTb |
| Broche 12 | PTA5 — RESET_b |
| Broche 13 | PTA6 — GPIO / FTM0_CH3 / I2S_RX_BCLK |
| Broche 14 | PTA7 — GPIO / FTM0_CH4 / I2S_RX_FS |
| Broche 15 | PTA8 — GPIO / FTM0_CH5 / I2S_RX_MCLK |
| Broche 16 | PTA9 — GPIO / FTM0_CH6 / I2S_RX_D |
| Broche 17 | PTA10 — GPIO / FTM2_CH0 / I2S_TX_BCLK |
| Broche 18 | PTA11 — GPIO / FTM2_CH1 / I2S_TX_D |
| Broche 19 | PTA12 — GPIO / FTM2_CH2 / I2S_TX_FS |
| Broche 20 | PTA13 — GPIO / FTM2_CH3 / I2S_TX_MCLK |
| Broche 21 | PTA14 — GPIO / FTM1_CH0 / I2S_CLKIN |
| Broche 22 | PTA15 — GPIO / FTM1_CH1 / I2S_CLKIN |
| Broche 23 | PTA16 — GPIO / SPI0_SIN / FTM0_CH5 |
| Broche 24 | PTA17 — GPIO / SPI0_SOUT / FTM0_CH6 |
| Broche 25 | PTA18 — GPIO / SPI0_SCK / FTM0_CH7 |
| Broche 26 | PTA19 — GPIO / SPI0_PCS0 / FTM2_FLT3 |
| Broche 27 | VDD — Digital supply voltage |
| Broche 28 | VSS — Digital ground |
| Broche 29 | PTC0 — GPIO / FTM0_CH0 / EXTRG_IN |
| Broche 30 | PTC1 — GPIO / FTM0_CH1 / EXTRG_IN |
| Broche 31 | PTC2 — GPIO / FTM0_CH2 / CMP1_OUT |
| Broche 32 | PTC3 — GPIO / FTM0_CH3 / CMP2_OUT |
| Broche 33 | PTC4 — GPIO / FTM0_CH4 / USB_SOF_OUT |
| Broche 34 | PTC5 — GPIO / FTM0_CH5 / CMP1_OUT |
| Broche 35 | PTC6 — GPIO / FTM0_CH6 / CMP2_OUT |
| Broche 36 | PTC7 — GPIO / FTM0_CH7 / CMP3_OUT |
| Broche 37 | PTC8 — GPIO / FTM3_CH4 / ADC1_SE8 |
| Broche 38 | PTC9 — GPIO / FTM3_CH5 / ADC1_SE9 |
| Broche 39 | PTC10 — GPIO / FTM3_CH6 / ADC1_SE10 |
| Broche 40 | PTC11 — GPIO / FTM3_CH7 / ADC1_SE11 |
| Broche 41 | PTC12 — GPIO / FTM3_CH0 / ADC1_SE12 |
| Broche 42 | PTC13 — GPIO / FTM3_CH1 / ADC1_SE13 |
| Broche 43 | PTC14 — GPIO / FTM3_CH2 / ADC1_SE14 |
| Broche 44 | PTC15 — GPIO / FTM3_CH3 / ADC1_SE15 |
| Broche 45 | PTC16 — GPIO / FTM3_CH4 / ADC1_SE16 |
| Broche 46 | PTC17 — GPIO / FTM3_CH5 / ADC1_SE17 |
| Broche 47 | PTC18 — GPIO / FTM3_CH6 / ADC1_SE18 |
| Broche 48 | PTC19 — GPIO / FTM3_CH7 / ADC1_SE19 |
| Broche 49 | VDD — Digital supply voltage |
| Broche 50 | VSS — Digital ground |
| Broche 51 | PTD0 — GPIO / FTM0_CH0 / SPI1_PCS0 |
| Broche 52 | PTD1 — GPIO / FTM0_CH1 / SPI1_SCK |
| Broche 53 | PTD2 — GPIO / FTM0_CH2 / SPI1_SOUT |
| Broche 54 | PTD3 — GPIO / FTM0_CH3 / SPI1_SIN |
| Broche 55 | PTD4 — GPIO / FTM0_CH4 / SPI1_PCS1 |
| Broche 56 | PTD5 — GPIO / FTM0_CH5 / SPI1_PCS2 |
| Broche 57 | PTD6 — GPIO / FTM0_CH6 / SPI1_PCS3 |
| Broche 58 | PTD7 — GPIO / FTM0_CH7 / CMP1_OUT |
| Broche 59 | PTD8 — GPIO / FTM1_CH0 / I2C0_SCL |
| Broche 60 | PTD9 — GPIO / FTM1_CH1 / I2C0_SDA |
| Broche 61 | PTD10 — GPIO / FTM1_CH2 / I2C1_SCL |
| Broche 62 | PTD11 — GPIO / FTM1_CH3 / I2C1_SDA |
| Broche 63 | PTD12 — GPIO / FTM1_CH4 / FTM3_FLT1 |
| Broche 64 | PTD13 — GPIO / FTM1_CH5 / FTM3_FLT2 |
| Broche 65 | PTD14 — GPIO / FTM1_CH6 / FTM3_FLT3 |
| Broche 66 | PTD15 — GPIO / FTM1_CH7 / FTM0_FLT3 |
| Broche 67 | PTD16 — GPIO / FTM0_CH0 / UART2_TX |
| Broche 68 | PTD17 — GPIO / FTM0_CH1 / UART2_RX |
| Broche 69 | PTD18 — GPIO / FTM0_CH2 / UART2_RTS_b |
| Broche 70 | PTD19 — GPIO / FTM0_CH3 / UART2_CTS_b |
| Broche 71 | VDD — Digital supply voltage |
| Broche 72 | VSS — Digital ground |
| Broche 73 | PTE0 — GPIO / FTM1_CH0 / I2S_CLKIN |
| Broche 74 | PTE1 — GPIO / FTM1_CH1 / I2S_RXD0 |
| Broche 75 | PTE2 — GPIO / FTM1_CH2 / I2S_RX_FS |
| Broche 76 | PTE3 — GPIO / FTM1_CH3 / I2S_RX_BCLK |
| Broche 77 | PTE4 — GPIO / FTM2_CH0 / SPI2_PCS0 |
| Broche 78 | PTE5 — GPIO / FTM2_CH1 / SPI2_SCK |
| Broche 79 | PTE6 — GPIO / FTM2_CH2 / SPI2_SOUT |
| Broche 80 | PTE7 — GPIO / FTM2_CH3 / SPI2_SIN |
| Broche 81 | PTE8 — GPIO / FTM2_CH4 / UART5_TX |
| Broche 82 | PTE9 — GPIO / FTM2_CH5 / UART5_RX |
| Broche 83 | PTE10 — GPIO / FTM2_CH6 / I2C2_SCL |
| Broche 84 | PTE11 — GPIO / FTM2_CH7 / I2C2_SDA |
| Broche 85 | PTE12 — GPIO / FTM3_CH0 / SPI2_PCS1 |
| Broche 86 | PTE13 — GPIO / FTM3_CH1 / SPI2_PCS2 |
| Broche 87 | PTE14 — GPIO / FTM3_CH2 / SPI2_PCS3 |
| Broche 88 | PTE15 — GPIO / FTM3_CH3 / I2S_TXD0 |
| Broche 89 | PTE16 — GPIO / UART4_TX / CMP3_OUT |
| Broche 90 | PTE17 — GPIO / UART4_RX / CMP2_OUT |
| Broche 91 | PTE18 — GPIO / UART4_RTS_b / CMP1_OUT |
| Broche 92 | PTE19 — GPIO / UART4_CTS_b / CMP0_OUT |
| Broche 93 | VDD — Digital supply voltage |
| Broche 94 | VSS — Digital ground |
| Broche 95 | USB0_DP — USB D+ (Full-Speed with on-chip PHY) |
| Broche 96 | USB0_DM — USB D- (Full-Speed with on-chip PHY) |
| Broche 97 | VOUT33 — USB 3.3 V regulator output (bypass required) |
| Broche 98 | VREGIN — USB regulator input |
| Broche 99 | USB0_VBUS — USB VBUS detect |
| Broche 100 | USB0_ID — USB OTG ID (host vs device detect) |
| Broche 101 | RTC_XTAL32 — 32 kHz RTC crystal input |
| Broche 102 | RTC_XTAL32B — 32 kHz RTC crystal output |
| Broche 103 | VDD — Digital supply voltage |
| Broche 104 | VSS — Digital ground |
| Broche 105 | TAMPER0 — Tamper detect pin 0 |
| Broche 106 | TAMPER1 — Tamper detect pin 1 |
| Broche 107 | TAMPER2 — Tamper detect pin 2 |
| Broche 108 | TAMPER3 — Tamper detect pin 3 |
| Broche 109 | TAMPER4 — Tamper detect pin 4 |
| Broche 110 | TAMPER5 — Tamper detect pin 5 |
| Broche 111 | TAMPER6 — Tamper detect pin 6 |
| Broche 112 | TAMPER7 — Tamper detect pin 7 |
| Broche 113 | ADC0_DP0 — ADC0 differential pair 0 input (P-side) |
| Broche 114 | ADC0_DM0 — ADC0 differential pair 0 input (N-side) |
| Broche 115 | ADC0_DP1 — ADC0 differential pair 1 input (P-side) |
| Broche 116 | ADC0_DM1 — ADC0 differential pair 1 input (N-side) |
| Broche 117 | ADC1_DP0 — ADC1 differential pair 0 input (P-side) |
| Broche 118 | ADC1_DM0 — ADC1 differential pair 0 input (N-side) |
| Broche 119 | VDD — Digital supply voltage |
| Broche 120 | VSS — Digital ground |
| Broche 121 | DAC0_OUT — 12-bit DAC0 output |
| Broche 122 | DAC1_OUT — 12-bit DAC1 output |
| Broche 123 | VREFH — ADC high reference voltage input |
| Broche 124 | VREFL — ADC low reference voltage input |
| Broche 125 | VDDA — Analog supply voltage |
| Broche 126 | VSSA — Analog ground |
| Broche 127 | OSC0_XTAL — Main crystal oscillator input |
| Broche 128 | OSC0_EXTAL — Main crystal oscillator output |
| Broche 129 | RTC_WAKEUP_B — RTC wakeup output / tamper pin (alt) |
| Broche 130 | PTF0 — GPIO / FTM3_CH0 / I2S_TXD0 |
| Broche 131 | PTF1 — GPIO / FTM3_CH1 / I2S_TXD1 |
| Broche 132 | PTF2 — GPIO / FTM3_CH2 / I2S_RXD0 |
| Broche 133 | PTF3 — GPIO / FTM3_CH3 / I2S_RXD1 |
| Broche 134 | PTF4 — GPIO / FTM3_CH4 / I2S_RX_FS |
| Broche 135 | PTF5 — GPIO / FTM3_CH5 / I2S_RX_BCLK |
| Broche 136 | PTF6 — GPIO / FTM3_CH6 / I2S_TX_BCLK |
| Broche 137 | PTF7 — GPIO / FTM3_CH7 / I2S_TX_FS |
| Broche 138 | PTG0 — GPIO / FTM0_CH0 / I2S_TXD0 |
| Broche 139 | PTG1 — GPIO / FTM0_CH1 / I2S_TXD1 |
| Broche 140 | PTG2 — GPIO / FTM0_CH2 / I2S_RXD0 |
| Broche 141 | PTG3 — GPIO / FTM0_CH3 / I2S_RXD1 |
| Broche 142 | PTG4 — GPIO / FTM0_CH4 / I2S_RX_FS |
| Broche 143 | PTG5 — GPIO / FTM0_CH5 / I2S_RX_BCLK |
| Broche 144 | PTG6 — GPIO / FTM0_CH6 / I2S_TX_BCLK |
Applications typiques
MK21FN1M0VLQ12 convient pour 6 applications: USB-Connected Secure Industrial Sensors, Point-of-Sale Terminals with Hardware Crypto, Smart Electricity Meters with Tamper Detection, Secure Building Automation Gateways, Wearable Health Monitors (Non-FDA Class), Low-Power Segment-LCD HMI Controllers.
USB-Connected Secure Industrial Sensors
Why MK21FN1M0VLQ12 fits: The 120 MHz Cortex-M4 with FPU runs USB 2.0 Full-Speed stacks with on-chip PHY, while hardware AES-128 and tamper pins protect telemetry against software and physical attacks. 1 MB Flash accommodates USB + TLS stacks; 128 KB SRAM buffers continuous measurement streams. Usage and performance: Place the MCU between a 24 V-to-3.3 V industrial rail and the USB D+/D- lines; ensure 90 ohm differential routing, a common-mode choke, and ESD protection. The MK21FN1M0VLQ12 trades Ethernet for lower USB power draw, ideal for low-volume secure sensor nodes, while the MK24FN1M0 variant is a marginal upgrade if HS USB is later required.
Recommandé
Point-of-Sale Terminals with Hardware Crypto
Why MK21FN1M0VLQ12 fits: Hardware AES-128 accelerators and tamper-detection pins enable PCI-PTS-style secure key storage on the same silicon; 1 MB Flash stores PIN handling, contactless, and crypto firmware. 120 MHz Cortex-M4 with FPU runs DES, AES, RSA helpers fast enough for EMV contactless transactions. Usage and performance: Use Secure JTAG disabled pin to keep debug port locked in production, route tamper pins to enclosure intrusion mesh, and run BIST at boot. The MK24FN1M0 variant is the right swap only if a future migration to HS USB peripherals is planned.
Recommandé
Smart Electricity Meters with Tamper Detection
Why MK21FN1M0VLQ12 fits: The K21F adds dedicated tamper pins for magnetic and physical intrusion alarms, plus a 16-bit SAR ADC with adequate channels for voltage, current, and temperature sensors. 128 KB SRAM holds metering accumulators with headroom for DLMS/COSEM stacks, and 1 MB Flash stores firmware and calibration tables. Usage and performance: The MCU fits the 1.71-3.6 V supply range typical of battery-buffered meters and offers low-power Stop mode for black-out conditions. Pick MK22FN1M0VLQ12 if a segment-LCD display replaces the LED matrix without changing the surrounding footprint.
Recommandé
Secure Building Automation Gateways
Why MK21FN1M0VLQ12 fits: USB OTG with on-chip PHY lets the gateway expose a USB mass-storage slot for firmware updates or a USB cellular dongle for backup connectivity. Hardware AES-128 secures local BACnet/Modbus communications; tamper pins detect panel opening. 1 MB Flash holds multi-protocol stacks including BACnet, KNX, and TLS. Usage and performance: Power the MCU from 24 V building bus via an LDO and route USB to Type-A or micro-B depending on housing. The MK21FN1M0VLQ12 keeps current draw modest, but when adding HS peripherals, switch to MK24FN1M0VLQ12 with hardware-compatible footprint.
Recommandé
Wearable Health Monitors (Non-FDA Class)
Why MK21FN1M0VLQ12 fits: 120 MHz Cortex-M4 with DSP extensions runs HRV and step-count DSP filters; 128 KB SRAM keeps time-series windows; full-speed USB eases tethered charging and data offload. Hardware crypto and tamper pins protect biometric data at rest. Usage and performance: Place the MCU on a 1.8 V rail to take advantage of low-voltage Stop mode below 200 uA; this trims wearable battery budget. For lighter applications where LCD driving is the priority, MK22FN1M0VLQ12 may be selected without sacrificing the same 144-LQFP PCB layout.
Recommandé
Low-Power Segment-LCD HMI Controllers
Why MK21FN1M0VLQ12 fits: Although the LCD controller is more pronounced on the K22 family, K21F still supports segment LCD driving for simple dash displays and panel meters. 1 MB Flash stores complex graph state-machines; 120 MHz handles USB-to-LCD bridging. Usage and performance: Choose this application as a fall-back only when K22 LCD is over-spec, otherwise prefer MK22FN1M0VLQ12 for the same 144-LQFP PCB. Trade-off: K22 routes fewer pins to GPIO but adds segmented display bias generation; the K21 family keeps the GPIO-heavy secure-application footprint.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MK21FN1M0VLQ12 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MK21FN1M0VLQ12R | MK22FN1M0AVLQ12 | MK24FN1M0VLQ12 | MK22FN1M0VLQ12 | MK24FN1M0VLQ12R |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 144-LQFP (20x20) | 144-LQFP (20x20) | 144-LQFP (20x20) | 144-LQFP (20x20) | 144-LQFP (20x20) | 144-LQFP (20x20) |
| Core | Cortex-M4 with FPU | Cortex-M4 with FPU | Cortex-M4 with FPU | Cortex-M4 with FPU | Cortex-M4 with FPU | Cortex-M4 with FPU |
| Max Clock | 120 MHz | 120 MHz | 120 MHz | 120 MHz | 120 MHz | 120 MHz |
| Flash | 1 MB | 1 MB | 1 MB | 1 MB | 1 MB | 1 MB |
| SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
Principaux différenciateurs
- Hardware AES-128 and tamper pins on-chip (vs MK22FN1M0AVLQ12)
- Pin-compatible upgrade path to High-Speed USB (vs MK24FN1M0VLQ12)
- On-chip full-speed USB PHY (no external ULPI chip) (vs MK60 series (NRND/legacy))
Notes de conception
Estimated: For a 144-pin 0.5 mm pitch LQFP, the standard NXP K-series decouple recipe is one 100 nF X7R per VDD/VSS pair plus 4.7 uF X5R bulk within ~10 mm. With about 8 VDD pins on this package the cap count is roughly 9. Without this, MCORE ripple can corrupt ADC readings and corrupt USB 2.0 eye tests.
USB 2.0 Full-Speed D+/D- must be 90 ohm differential over a continuous ground plane with no stubs; include a common-mode choke and a transient suppressor. Without these, full-speed eye diagrams fail compliance and full-speed enumeration may fail at the host. NXP provides a dedicated Application Note for K2x USB layout that should be followed exactly.
The MK21FN1M0VLQ12 is NRND, so production orders must be confirmed against the latest NXP PCN stream before lock-in. Failing to do this may trap a design into a 1-year Last-Time-Buy if demand suddenly contracts; pair the part with MK24FN1M0 as a footprint-compatible second-source and keep firmware portable between the two.
Estimated: at maximum 120 MHz, the K21F typically draws about 30 mA with peripherals active, so dissipation stays under 0.1 W at 3.3 V. Theta_JA on 144-LQFP is around 50-55 C/W on a 4-layer JEDEC test board with adequate vias - well within safety - but a small copper pour on VDD/VSS pairs is recommended for cold-swap transients.
Informations de conformité
MK21FN1M0VLQ12 ships in a lead-free 144-LQFP that is RoHS-compliant; reach, halogen-free, and conflict-minerals declarations are not present in the verified web data and should be requested from NXP product compliance if required.
