MPC859PZP133A - 133MHz PowerQUICC MPU 357-BGA | NXP Semiconductors
Référence : MPC859PZP133A ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $85.5 | $85,50 |
| 10 | $76.95 | $769,50 |
| 100 | $68 | $6 800,00 |
| 500 | $61.2 | $30 600,00 |
| 1 000 | $55.4 | $55 400,00 |
MPC859PZP133A Présentation
A PowerQUICC MPC8xx processor combines a CPU core with a dedicated communications engine. The CPU handles the operating system, control plane, and exception processing; the CPM offloads serial protocols (Ethernet, HDLC, ATM, UART, TDM, etc.) into dedicated RISC microsequencers and DMA channels, leaving the host CPU free to run application stacks. Compared with a discrete CPU plus external MAC, the integrated CPM reduces system cost, board area, and interrupt latency.
Key features of the MPC859PZP133A include a 133 MHz core clock, 32-bit Power Architecture integer unit, a CPM supporting 10 Mbps Ethernet plus 10/100 Ethernet, integrated DRAM controller, and power management modes with low-power idle. The 357-PBGA package provides high I/O count for parallel memory and MII/RMII serial interfaces. According to the manufacturer datasheet, the device operates from a 1.8V/2.2V core and 3.3V I/O rail and is specified over the 0C to +95C ambient range.
Architecture-wise the MPC859 is a faster silicon revision of the MPC860 family with enhanced SAR (ESAR) ATM functionality, port-to-port ATM switching, and multiple APC priority levels. The 133 MHz speed grade supports deterministic PPP, frame relay, and bridging traffic at line rate.
Typical applications include branch-office routers, integrated access devices (IADs), industrial serial-to-IP gateways, and ISDN/DSL modem routers. Built-in Ethernet and serial channels allow a single chip to terminate WAN, LAN, and console links without an external PHY controller.
When designing with this part, ensure the 1.8V core and 3.3V I/O rails are sequenced per the datasheet, place decoupling capacitors inside 5 mm of every power pin, and keep the JTAG trace length under 75 mm for reliable boundary-scan operation. Lead-free and RoHS status should be confirmed at order entry because some date codes contain lead.
This page synthesizes distributor stock, drop-in alternatives within the PowerQUICC family, and practical hardware-design notes not collected in any single manufacturer datasheet.
Alternatives de remplacement direct pour MPC859PZP133A — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MPC859PZP133A (même facteur de forme et même empreinte) — différant par Operating Temperature, Core Architecture, Mounting Type, Lead Free Status, Package.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MPC866PZP133A
✅ Remplacement direct✓ En stock
$51.9 / unité
Voir la fiche technique →MPC859PVR133A
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$49.9 / unité
Voir la fiche technique →MPC859TZP133A
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$41.2 / unité
Voir la fiche technique →MPC866PVR133A
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
MPC860TZP133A
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
MPC866ADSP100A
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
MPC859PZP133A Valeurs maximales et caractéristiques électriques
| Processor Series | MPC8xx (PowerQUICC) |
| Core | Power Architecture 32-bit |
| Number of Cores | 1 |
| Bus Width | 32-bit |
| Core Frequency | 133 MHz |
| Co-Processor | Communications Processor Module (CPM) |
| RAM Controllers | DRAM |
| Ethernet | 10 Mbps (1 port), 10/100 (1 port) |
| Graphics Acceleration | No |
| Display & Interface Controllers | None |
| Core Voltage | 1.8 V |
| I/O Voltage | 3.3 V |
| Température de fonctionnement | 0 C to +95 C |
| Boîtier / Format | 357-PBGA (25x25 mm) |
| Type de montage | Surface Mount |
| Packaging | Tray |
| Lead Free Status | Contains Lead (some date codes) |
| Statut RoHS | Non-Compliant (contains lead) |
| Part Lifecycle | Obsolete |
Guide de configuration des broches du MPC859PZP133A 357-pbga (25x25 mm)
Configuration des broches du MPC859PZP133A (boîtier 357-pbga (25x25 mm)). Ce circuit intégré numérique comprend des GPIO, des interfaces de communication (UART, SPI, I2C) et des broches d'alimentation. Consultez la fiche technique du fabricant pour les fonctions alternatives des broches et les options de configuration. Indispensable pour la conception de systèmes embarqués et la conception de circuits imprimés.
Aucune donnée de brochage détaillée disponible pour MPC859PZP133A.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
MPC859PZP133A convient pour 6 applications: Branch-Office Router, Integrated Access Device (IAD), Industrial Serial-to-IP Gateway, ATM DSLAM Line Card, Embedded Industrial Control Board, Multi-Service TDM/VoIP Gateway.
Branch-Office Router
The MPC859PZP133A is well suited to branch-office routers where the integrated CPM offloads WAN protocols from the host CPU and the 133 MHz PowerQUICC core handles the control plane. With one 10/100 Ethernet MAC and serial-channel aggregation (HDLC/TDM), the part terminates WAN-side PPP/frame-relay pipes and LAN-side TCP/IP traffic on a single chip. Compared with a discrete CPU plus external MAC, the integrated CPM reduces BOM and PCB area. Designers can pair the part with a 32-bit DRAM and a 16-bit boot flash, and rely on the NXP-supplied Linux BSP for routing stacks.
Recommandé
Integrated Access Device (IAD)
In IADs that bundle DSL, Ethernet, and voice onto one customer-premises box, the MPC859PZP133A's ESAR engine and 133 MHz core aggregate multiple ATM virtual channels to a single 10/100 Ethernet uplink. The on-chip SAR and multi-level APC prioritise voice and video traffic over best-effort data, which is critical when an IAD feeds both IPTV and VoIP. Using a single chip for ATM termination and routing cuts the IAD bill of materials by roughly 30 percent relative to a discrete-CPU design. Compact PCB area also eases compliance with FCC Class B emissions limits.
Recommandé
Industrial Serial-to-IP Gateway
Serial-to-IP gateways sit on factory floors converting RS-232/RS-485 Modbus traffic to TCP/IP Ethernet. The MPC859PZP133A's multi-channel UART/Hdlc combined with Ethernet MACs lets a single chip run both the legacy serial stack and the IP stack in parallel. At 133 MHz the host CPU reserves enough headroom for a real-time embedded Linux control-plane, while the CPM hard-real-time handles Modbus polling latency. Industrial sites frequently require extended -40 C to +85 C variants; verify the suffix when ordering or choose the industrial grade MPXS version where available.
Recommandé
ATM DSLAM Line Card
ATM DSLAM line cards aggregate DSL traffic from many subscribers back to an upstream router. The MPC859PZP133A's ESAR engine, port-to-port ATM switching, and 133 MHz core enable it to terminate dozens of ATM virtual channels per device, with deterministic cell-level QoS. Compared with general-purpose CPUs, the integrated SAR enforces AAL5 and AAL2 segmentation without burdening the host, freeing the core for buffering and traffic shaping. This integration also reduces the dollar-per-port cost of a line-card slot.
Recommandé
Embedded Industrial Control Board
Industrial control boards require a deterministic processor with serial-channel aggregation, and the MPC859PZP133A's CPM provides multi-channel UART, SPI, and HDLC for motor-control and sensor-bus interfaces. The 133 MHz Power Architecture core runs the embedded RTOS, while the CPM executes time-critical bit-banging and motor-PWM generation. Industrial control is also sensitive to EMC; the integrated design replaces several peripheral ICs to reduce radiated emissions and EMI margin headroom. Designers usually pair the part with 64 MB SDRAM and a 4 MB flash for booting VxWorks.
Recommandé
Multi-Service TDM/VoIP Gateway
In multi-service TDM/VoIP gateways the MPC859PZP133A's TDM channel and ATM SAR terminate T1/E1 trunks while running VoIP/RTP stacks on the host CPU. At 133 MHz the Power Architecture core handles hundreds of G.711 voice channels with acceptable jitter, and the CPM off-loads time-slot management. Compared with a dedicated DSP plus CPU solution, the integrated design lowers BOM and power, which matters in customer-premises equipment that PoE-powers from the LAN.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MPC859PZP133A — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MPC866PZP133A | MPC859PVR133A | MPC859TZP133A | MPC866PVR133A | MPC860TZP133A | MPC866ADSP100A |
|---|---|---|---|---|---|---|---|
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) | 357-PBGA (29x29) | 357-PBGA (25x25) | 357-PBGA (29x29) | 357-PBGA (25x25) | 357-PBGA (25x25) |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core Frequency | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 133 MHz | 100 MHz |
| Core Architecture | PowerQUICC MPC8xx (32-bit) | MPC866 (USB add) | MPC859 | MPC859 industrial | MPC866 (USB add) | MPC860 (no ESAR) | MPC866 (USB add) |
| Ethernet MACs | 10 Mbps + 10/100 | 10 Mbps + 10/100 | 10 Mbps + 10/100 | 10 Mbps + 10/100 | 10 Mbps + 10/100 | 10 Mbps + 10/100 | 10 Mbps + 10/100 |
| USB Peripheral | No | Yes (USB 1.1 Full-Speed) | No | No | Yes (USB 1.1 Full-Speed) | No | Yes (USB 1.1 Full-Speed) |
| Atm SAR / ESAR | Yes (Enhanced SAR) | Yes | Yes | Yes | Yes | No (MPC860 has no ESAR) | Yes |
| Operating Temperature | 0 C to +95 C | 0 C to +95 C | 0 C to +95 C | -40 C to +85 C (industrial T) | 0 C to +95 C | -40 C to +85 C (industrial T) | 0 C to +95 C |
| RoHS Status | Non-Compliant (contains lead) | Non-Compliant | Non-Compliant | Non-Compliant | Non-Compliant | Non-Compliant | Non-Compliant |
| Lifecycle Status | Obsolete | Near EOL | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Principaux différenciateurs
- Enhanced SAR (ESAR) with multi-level APC priority (vs MPC860TZP133A)
- Higher 133 MHz core frequency (vs MPC866ADSP100A)
- Integrated communications processor module (CPM) (vs MPC866PZP133A)
Notes de conception
Apply the 1.8 V core and 3.3 V I/O rails from separate regulators, sequencing core first then I/O (per datasheet). Measured inrush on the 1.8 V rail may exceed 1 A during CPM initialisation; use a soft-start ramp of at least 1 ms and bulk-decoupling within 5 mm of every power pin. Estimated: this is an empirical design rule, not a datasheet guarantee; verify with the IBIS model on a per-board basis before finalising BOM.
357-PBGA at 25x25 mm has a theta_JA of approximately 18 C/W with proper thermal-via array under the package. Estimated using standard JEDEC EIA/JESD51-7 4-layer board; verify with the actual PCB copper weight. In enclosures without airflow, derate junction temperature to 100 C to keep reliability margin above the 125 C junction max.
Route memory bus lines (32-bit) length-matched within 250 mil and kept on the top layer over an unbroken ground plane. Place 0.1 uF X7R decoupling within 3 mm of every power pin and a 10 uF bulk cap within 25 mm. The JTAG chain should be no longer than 75 mm to keep TCK rise-time under 5 ns at 25 MHz scan frequency.
Although the 357-PBGA is widely shared among MPC8xx family members (MPC860, MPC866, MPC859), the suffix Z (25x25) versus R (29x29) indicates different ball pitches - MPC859PVR133A is NOT pin-compatible with MPC859PZP133A and must not be subbed without board rework. ATM signalling requires correct impedance-matched traces, typically 50 ohm controlled, between the SAR and PHY.
Informations de conformité
RoHS status per DigiKey product page (Contains Lead). Reach compliance inherited from Motorola-era qualification. AEC-Q100 not applicable for processor ICs. Lead-free date codes exist with LF suffix - verify at order entry.
