PIC32MX130F128H-V/MR - 32-bit MCU, 128KB Flash, 64-QFN | Microchip
Référence : PIC32MX130F128H-V/MR ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $6.4 | $6,40 |
| 10 | $5.76 | $57,60 |
| 100 | $5.12 | $512,00 |
| 500 | $4.61 | $2 305,00 |
| 1 000 | $4.1 | $4 100,00 |
PIC32MX130F128H-V/MR Présentation
A PIC32MX microcontroller is a 32-bit MIPS-based MCU from Microchip's PIC32 family, sitting between 16-bit PIC24/dsPIC and 32-bit ARM Cortex-M devices. It combines a Harvard-architecture M4K core with rich peripherals such as USB, CAN, I2S, PMP, and Peripheral Pin Select (PPS) routing, making it a versatile choice for connectivity, graphical, and real-time control applications.
Key features of the PIC32MX130F128H-V/MR include up to 50 MHz / 83 DMIPS core performance, two I2S and four SPI modules for codec and serial communications, Peripheral Pin Select (PPS) for flexible peripheral-to-pin mapping, Parallel Master Port (PMP) with dual buffers for graphics interfaces, a 10-bit 1 Msps ADC with up to 13 channels, and an mTouch capacitive-touch peripheral for touch-sensing user input. The 128 KB Flash supports large application firmware with library overhead.
Architecturally, the device integrates a 5-stage pipeline M4K core with single-cycle multiplication, a prefetch cache to accelerate Flash execution, an 8-channel DMA controller for low-CPU-overhead data movement, and a 10-bit 1 Msps analog-to-digital converter. The 2.5V/3.3V dual-voltage core with on-chip regulator simplifies single-supply 3.3V designs while maintaining low active power consumption typical of the PIC32MX1xx family.
Typical applications include automotive body and infotainment subsystems, industrial HMI panels with PMP-driven LCDs, USB peripherals such as HID and CDC class devices, IoT sensor nodes, audio playback products using I2S DACs, and capacitive-touch user interfaces. The wide operating temperature range and AEC-Q100 qualification support under-hood and dashboard deployments.
When designing with this MCU, allocate the 128 KB Flash budget between bootloader, application, and library code early; PPS reassignment must be configured in code at startup to avoid pin conflicts; the QFN EP requires thermal via stitching under the exposed pad for reliable heat dissipation in industrial/automotive environments.
This page synthesizes distributor pricing, drop-in PIC32MX alternatives, PPS-aware design notes, and AEC-Q100 qualification context not found aggregated on any single manufacturer page.
Alternatives de remplacement direct pour PIC32MX130F128H-V/MR — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec PIC32MX130F128H-V/MR (même facteur de forme et même empreinte) — différant par ADC, Package, Operating Temperature, Core Architecture, Program Memory (Flash).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
PIC32MX130F128HT-V/MR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
PIC32MX130F128H-I/MR
✅ Remplacement direct✓ En stock
$3.05 / unité
Voir la fiche technique →PIC32MX130F256H-V/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
PIC32MX130F128H-V/PT
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
PIC32MX150F128H-V/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
PIC32MX130F064H-V/MR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
PIC32MX130F128H-V/MR Valeurs maximales et caractéristiques électriques
| Core Architecture | MIPS32 M4K 32-bit RISC |
| Maximum CPU Frequency | 50 MHz |
| Core Performance | 83 DMIPS |
| Program Flash | 128 KB (128K x 8) |
| Data SRAM | 16 KB |
| Operating Voltage | 2.3 V to 3.6 V |
| I/O Voltage | 3.3 V |
| ADC | 10-bit, up to 13 channels, 1 Msps |
| SPI Modules | 4 |
| I2S Modules | 2 |
| Peripheral Pin Select (PPS) | Yes |
| Parallel Master Port (PMP) | Yes, dual buffers |
| DMA Channels | 8 |
| Température de fonctionnement | -40 C to +105 C (V grade) |
| Boîtier | 64-QFN (MR), 9x9 mm with exposed pad |
| AEC-Q100 Qualification | Yes |
| Type de montage | Surface Mount |
Configuration des broches de PIC32MX130F128H-V/MR
| Broche 1 | RPB0/AN0/C1IN+/VBUSON — PPS-mappable I/O, ADC analog input 0 |
| Broche 2 | RPB1/AN1/C1IN- — PPS-mappable I/O, ADC analog input 1 |
| Broche 3 | RPB2/AN2/C2IN+/CVREF- — PPS-mappable I/O, ADC analog input 2 |
| Broche 4 | RPB3/AN3/C2IN-/CVREF+ — PPS-mappable I/O, ADC analog input 3 |
| Broche 5 | RPB4/AN4/C1OUT — PPS-mappable I/O, ADC analog input 4 |
| Broche 6 | RPB5/AN5/C2OUT — PPS-mappable I/O, ADC analog input 5 |
| Broche 7 | RPC0/PMA6/INT0 — PPS-mappable I/O, PMP address 6, external interrupt 0 |
| Broche 8 | RPC1/PMA7 — PPS-mappable I/O, PMP address 7 |
| Broche 9 | RPC2/PMA8 — PPS-mappable I/O, PMP address 8 |
| Broche 10 | RPC3/PMA9 — PPS-mappable I/O, PMP address 9 |
| Broche 11 | RPC4/PMA10 — PPS-mappable I/O, PMP address 10 |
| Broche 12 | RPC5/PMA11 — PPS-mappable I/O, PMP address 11 |
| Broche 13 | RPC6/PMA12 — PPS-mappable I/O, PMP address 12 |
| Broche 14 | RPC7/PMA13 — PPS-mappable I/O, PMP address 13 |
| Broche 15 | RPC8/PMA14 — PPS-mappable I/O, PMP address 14 |
| Broche 16 | RPC9/PMA15 — PPS-mappable I/O, PMP address 15 |
| Broche 17 | VSS — Ground |
| Broche 18 | VDD — Digital supply voltage 2.3V to 3.6V |
| Broche 19 | AVSS — Analog ground |
| Broche 20 | AVDD — Analog supply voltage |
| Broche 21 | RPB6/AN6/PGC2 — PPS-mappable I/O, ADC input 6, programming clock 2 |
| Broche 22 | RPB7/AN7/PGD2 — PPS-mappable I/O, ADC input 7, programming data 2 |
| Broche 23 | RPB8/AN8/CVREF+ — PPS-mappable I/O, ADC input 8 |
| Broche 24 | RPB9/AN9/CVREF- — PPS-mappable I/O, ADC input 9 |
| Broche 25 | RPB10/AN10 — PPS-mappable I/O, ADC input 10 |
| Broche 26 | RPB11/AN11 — PPS-mappable I/O, ADC input 11 |
| Broche 27 | VSS — Ground |
| Broche 28 | VDD — Digital supply voltage 2.3V to 3.6V |
| Broche 29 | RPD0/PMD0/OC1 — PPS-mappable I/O, PMP data 0, output compare 1 |
| Broche 30 | RPD1/PMD1/OC2 — PPS-mappable I/O, PMP data 1, output compare 2 |
| Broche 31 | RPD2/PMD2/OC3 — PPS-mappable I/O, PMP data 2, output compare 3 |
| Broche 32 | RPD3/PMD3/OC4 — PPS-mappable I/O, PMP data 3, output compare 4 |
| Broche 33 | RPD4/PMD4/OC6 — PPS-mappable I/O, PMP data 4, output compare 6 |
| Broche 34 | RPD5/PMD5/OC7 — PPS-mappable I/O, PMP data 5, output compare 7 |
| Broche 35 | RPD6/PMD6 — PPS-mappable I/O, PMP data 6 |
| Broche 36 | RPD7/PMD7 — PPS-mappable I/O, PMP data 7 |
| Broche 37 | RPD8/PMD8 — PPS-mappable I/O, PMP data 8 |
| Broche 38 | RPD9/PMD9 — PPS-mappable I/O, PMP data 9 |
| Broche 39 | RPD10/PMD10 — PPS-mappable I/O, PMP data 10 |
| Broche 40 | RPD11/PMD11 — PPS-mappable I/O, PMP data 11 |
| Broche 41 | VSS — Ground |
| Broche 42 | VDD — Digital supply voltage 2.3V to 3.6V |
| Broche 43 | RPE0/PMD12 — PPS-mappable I/O, PMP data 12 |
| Broche 44 | RPE1/PMD13 — PPS-mappable I/O, PMP data 13 |
| Broche 45 | RPE2/PMD14 — PPS-mappable I/O, PMP data 14 |
| Broche 46 | RPE3/PMD15 — PPS-mappable I/O, PMP data 15 |
| Broche 47 | RPE4/PMRD — PPS-mappable I/O, PMP read strobe |
| Broche 48 | RPE5/PMWR — PPS-mappable I/O, PMP write strobe |
| Broche 49 | RPE6/PMCS — PPS-mappable I/O, PMP chip select |
| Broche 50 | RPE7/PMALL/PMCS2 — PPS-mappable I/O, PMP address latch |
| Broche 51 | RPE8/PMBE — PPS-mappable I/O, PMP byte enable |
| Broche 52 | VSS — Ground |
| Broche 53 | VDD — Digital supply voltage 2.3V to 3.6V |
| Broche 54 | SDAO/RPF4/SDA2 — PPS-mappable I/O, I2C data |
| Broche 55 | SCKO/RPF5/SCL2 — PPS-mappable I/O, I2C clock |
| Broche 56 | PGEC1/AN12 — Programming clock 1, ADC input 12 |
| Broche 57 | PGED1/AN13 — Programming data 1, ADC input 13 |
| Broche 58 | VREF-/CVREF- — ADC negative reference |
| Broche 59 | VREF+/CVREF+ — ADC positive reference |
| Broche 60 | D+/RGPU — USB D+ data line with internal pull-up |
| Broche 61 | D- — USB D- data line |
| Broche 62 | VBUS — USB bus voltage detect |
| Broche 63 | VUSB3V3 — USB 3.3V supply |
| Broche 64 | MCLR — Master clear reset, drive low to reset |
Applications typiques
PIC32MX130F128H-V/MR convient pour 6 applications: Automotive Body and HMI Control, Industrial HMI with Graphical LCD, USB HID Peripheral Device, Audio Playback with I2S DAC, Capacitive Touch User Panel, IoT Sensor Node with Connectivity.
Automotive Body and HMI Control
The PIC32MX130F128H-V/MR is well suited for automotive body controllers and HMI subsystems due to its AEC-Q100 qualification, -40 C to +105 C V grade temperature range, and integrated 64-QFN MR footprint. Its 128 KB Flash supports communication stacks such as CAN and LIN plus body-control firmware, while the 16 KB SRAM handles control body loops with deterministic response. With PPS connectivity, the 50 MHz MIPS32 M4K core provides 83 DMIPS of performance to support bridge architecture, and the mTouch peripheral supports capacitive touch buttons on door handles or steering wheel interfaces. Unlike higher-end Cortex-M parts, the PIC32MX130 integrates USB, PMP, and touch in a single low-cost die.
Recommandé
Industrial HMI with Graphical LCD
The PIC32MX130F128H-V/MR drives industrial HMI panels with graphical LCDs through its Parallel Master Port (PMP) with dual read/write buffers, which can interface 8-bit or 16-bit LCD controllers directly without external logic. The 128 KB Flash supports graphics libraries, fonts, and multilingual strings, while the 16 KB SRAM holds frame buffers or runtime menus. The 64-QFN MR package keeps the PCB compact for handheld or panel-mount HMIs, and the V temperature grade supports factory floor enclosures. Place the device near the LCD connector with short PMP traces to maintain signal integrity at 50 MHz.
Recommandé
USB HID Peripheral Device
The PIC32MX130F128H-V/MR implements USB full-speed device class peripherals such as HID, CDC, and vendor-specific devices using its integrated USB 2.0 FS controller and 48 MHz USB clock domain. The 128 KB Flash fits USB stacks plus application logic, and the 16 KB SRAM holds USB endpoint buffers plus communication state. The 64-QFN MR package with PPS allows USB D+/D- to be routed to convenient pin locations, simplifying PCB stack-up. Unlike external USB interface chips, the PIC32MX130 integrates USB PHY and protocol in silicon, reducing BOM and PCB area.
Recommandé
Audio Playback with I2S DAC
The PIC32MX130F128H-V/MR drives I2S DACs for audio playback products through its two I2S modules and four SPI peripherals. The 128 KB Flash stores audio decoders, codec libraries, and UI code, while 16 KB SRAM handles decoded PCM buffers for short clips or streaming. The 50 MHz MIPS32 M4K core delivers enough processing headroom for low-bitrate audio codecs, and PPS allows the I2S bit-clock and word-select lines to be remapped to optimize PCB routing. Place 100 nF decoupling close to AVDD pins to keep DAC output noise low.
Recommandé
Capacitive Touch User Panel
Recommandé
IoT Sensor Node with Connectivity
The PIC32MX130F128H-V/MR acts as an IoT sensor aggregation node connecting sensors through I2C, SPI, or UART peripherals and forwarding data over USB, CAN, or a wireless companion module. The 128 KB Flash supports TLS or proprietary IoT stacks, while 16 KB SRAM holds short network buffers. The 50 MHz core and 8-channel DMA allow sensor data to be streamed with low CPU overhead, and PPS lets designers route peripheral pins to optimize antenna isolation. Pair with an external wireless module such as the RN2483 LoRa or ATWINC1500 Wi-Fi for full IoT connectivity.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour PIC32MX130F128H-V/MR — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | PIC32MX130F128HT-V/MR | PIC32MX130F128H-I/MR | PIC32MX130F256H-V/MR | PIC32MX150F128H-V/MR | PIC32MX130F064H-V/MR |
|---|---|---|---|---|---|---|
| Package | 64-QFN (MR, 9x9 mm) | 64-QFN (MR, 9x9 mm) - same | 64-QFN (MR, 9x9 mm) - same | 64-QFN (MR, 9x9 mm) - same | 64-QFN (MR, 9x9 mm) - same | 64-QFN (MR, 9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Program Flash | 128 KB | 128 KB | 128 KB | 256 KB | 128 KB | 64 KB |
| Data SRAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB |
| Maximum Frequency | 50 MHz | 50 MHz | 50 MHz | 50 MHz | 60 MHz | 50 MHz |
| Operating Temperature | -40 C to +105 C (V grade) | -40 C to +105 C (V grade) | -40 C to +85 C (I grade) | -40 C to +105 C (V grade) | -40 C to +105 C (V grade) | -40 C to +105 C (V grade) |
| Core Architecture | MIPS32 M4K | MIPS32 M4K | MIPS32 M4K | MIPS32 M4K | MIPS32 M4K | MIPS32 M4K |
| AEC-Q100 Qualified | Yes | Yes | Yes | Yes | Yes | Yes |
| USB | USB 2.0 FS device | USB 2.0 FS device | USB 2.0 FS device | USB 2.0 FS device | USB 2.0 FS device | USB 2.0 FS device |
Principaux différenciateurs
- AEC-Q100 automotive qualification (vs PIC32MX130F064H-V/MR)
- V temperature grade with mTouch peripheral (vs PIC32MX130F128H-I/MR)
- Lower flash but more cost effective than PIC32MX150 family (vs PIC32MX150F128H-V/MR)
Notes de conception
The 64-QFN MR package exposes a thermal pad (EP) on pin 65 (central pad) that must be soldered to a PCB thermal copper pad of at least 6 x 6 mm with an array of thermal vias (0.3 mm drill, 0.5 mm pitch) stitching to the inner ground plane. Failing to solder the EP results in 5-10 C higher junction temperature rise at full 50 MHz operation, which can derate the V temperature grade. Decoupling: place one 100 nF X7R 0402 within 1 mm of each VDD/AVDD pin pair, plus a bulk 4.7 uF X5R 0805 near the package.
PPS pin assignments must be unlocked by writing a specific sequence to CFGCON before any PPS register can be modified, otherwise the write is silently ignored. On the PIC32MX130F128H-V/MR, digital peripheral pins default to analog on reset and must be reconfigured via ANSEL register. Always include a 1 ms delay after releasing MCLR before the first GPIO write so that internal voltage regulators stabilize.
The USB D+ and D- pins (60 and 61) require a 45 ohm characteristic impedance on the differential pair and 15 kV ESD protection. Place the 1.5 kohm pull-up on D+ close to the MCU and route the pair over an unbroken ground plane. For automotive USB ports add a common-mode choke and TVS diode. The VUSB3V3 pin must be supplied with 3.3V from a low-noise LDO, not directly from VDD, to meet USB eye pattern compliance.
Informations de conformité
AEC-Q100 qualified per Hotenda distributor listing. RoHS and REACH compliant. Halogen-free per Microchip environmental certification.
