STM32H745ZGT6 - Dual Cortex-M7/M4 MCU 1MB Flash | STMicroelectronics
Référence : STM32H745ZGT6 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $23.39 | $23,39 |
| 10 | $21.42 | $214,20 |
| 100 | $18.95 | $1 895,00 |
| 500 | $17.1 | $8 550,00 |
| 1 000 | $15.6 | $15 600,00 |
STM32H745ZGT6 Présentation
As a microcontroller (MCU), the STM32H745ZGT6 sits in the broader taxonomy of embedded processing devices: MCU -> ARM Cortex-M MCU -> STM32 family -> STM32H7 high-performance series. It is a system-on-chip integrating CPU cores, memory, analog peripherals, and digital interfaces in a single package, programmed typically via STM32CubeIDE, STM32CubeMX, and the HAL/LL driver libraries.
Key differentiating features include the dual-core asymmetric architecture (M7 + M4) with separate instruction caches, an integrated SMPS step-down converter for core supply (improving efficiency versus external LDOs), up to 2 MB Flash and 1 MB RAM across the full H745 line, a Chrom-ART graphics accelerator, JPEG codec hardware, and an extensive peripheral set including 16-/12-bit ADCs, DACs, timers, Ethernet, USB, CAN FD, and high-speed SPI/QSPI interfaces for external memory or displays. The device operates from 1.62 V to 3.6 V with internal SMPS generating the core voltage.
Typical applications include industrial motor control (field-oriented control), audio amplifiers and DSP effects processors, HMI panels with TFT-LCD and touch, building automation, IoT edge gateways, programmable logic controllers, and medical instrumentation. The dual-core design enables deterministic real-time response on the M4 while the M7 executes complex algorithms without mutual blocking.
When designing with this part, allocate a minimum 4-layer PCB with continuous GND pour around the LQFP-144 package to manage thermal dissipation at high clock speeds. Decouple each VDD/VBAT pin with 100 nF X7R ceramic capacitors placed within 2 mm of the respective pins. Use STM32CubeMX to configure the SMPS inductor and feedback compensation to achieve the specified core voltage ripple under your worst-case load transient.
This page synthesizes distributor pricing, drop-in pin-compatible alternatives within the STM32H7 family, and practical PCB layout notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour STM32H745ZGT6 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
Aucune alternative de remplacement direct disponible pour ce produit.
Demander des alternativesSTM32H745ZGT6 Valeurs maximales et caractéristiques électriques
| Core Architecture | Dual-core Arm Cortex-M7 (480 MHz) + Cortex-M4 (240 MHz) |
| Instruction Set | 32-bit ARM Thumb-2 |
| Flash Memory | 1 MB (1M x 8) |
| Boîtier | 144-pin LQFP, 20x20 mm, 0.5 mm pitch |
| Operating Voltage | 1.62 V to 3.6 V (with internal SMPS for VCORE) |
| Supply Voltage Range | 1.8 V / 2.5 V / 3.3 V typical I/O rails |
| Max M7 Clock Frequency | 480 MHz |
| Max M4 Clock Frequency | 240 MHz |
| Internal SMPS | Yes (step-down converter for core supply) |
| Température de fonctionnement | -40C to +85C (industrial grade, grade 6) |
| Type de montage | Surface Mount |
| Communication Interfaces | Ethernet, USB OTG, CAN FD, SPI, QSPI, I2C, UART, SAI |
| Statut RoHS | Compliant (ECOPACK2) |
| Package Code (ST suffix) | ZGT6 = LQFP144 industrial grade, 1 MB Flash |
Configuration des broches de STM32H745ZGT6
| Broche 1 | PE2 — General-purpose I/O, TRACECLK |
| Broche 2 | PE3 — General-purpose I/O, TRACED0 |
| Broche 3 | PE4 — General-purpose I/O, TRACED1 |
| Broche 4 | PE5 — General-purpose I/O, TRACED2 |
| Broche 5 | PE6 — General-purpose I/O, TRACED3 |
| Broche 6 | VBAT — Backup battery / RTC supply input |
| Broche 7 | PC13 — GPIO, RTC_TAMP1, WKUP3 |
| Broche 8 | PC14 — GPIO, OSC32_IN |
| Broche 9 | PC15 — GPIO, OSC32_OUT |
| Broche 10 | VSS — Ground reference |
| Broche 11 | VDD — Main I/O supply (1.62-3.6 V) |
| Broche 12 | VREF+ — ADC positive reference voltage |
| Broche 13 | PA0 — GPIO, TIM2_CH1, ADC1_INP0 |
| Broche 14 | PA1 — GPIO, TIM2_CH2, ADC1_INP1 |
| Broche 15 | PA2 — GPIO, TIM2_CH3, USART2_TX |
| Broche 16 | PA3 — GPIO, TIM2_CH4, USART2_RX |
| Broche 17 | VSS — Ground reference |
| Broche 18 | VDD — Main I/O supply |
| Broche 19 | PA4 — GPIO, SPI1_NSS, USART2_CK |
| Broche 20 | PA5 — GPIO, SPI1_SCK, DAC1_OUT1 |
| Broche 21 | PA6 — GPIO, SPI1_MISO, TIM13_CH1 |
| Broche 22 | PA7 — GPIO, SPI1_MOSI, TIM14_CH1 |
| Broche 23 | PC4 — GPIO, USART3_TX, ADC1_INP4 |
| Broche 24 | PC5 — GPIO, USART3_RX, ADC1_INP5 |
| Broche 25 | PB0 — GPIO, TIM1_CH2N, ADC1_INP8 |
| Broche 26 | PB1 — GPIO, TIM1_CH3N, ADC1_INP9 |
| Broche 27 | PB2 — GPIO, SAI1_FS_A |
| Broche 28 | PF11 — GPIO, FMC A16 |
| Broche 29 | PF12 — GPIO, FMC A17 |
| Broche 30 | VSS — Ground reference |
| Broche 31 | VDD — Main I/O supply |
| Broche 32 | PB10 — GPIO, I2C2_SCL, USART3_TX |
| Broche 33 | PB11 — GPIO, I2C2_SDA, USART3_RX |
| Broche 34 | VSS — Ground reference |
| Broche 35 | VDD — Main I/O supply |
| Broche 36 | PB12 — GPIO, SPI2_NSS, USART3_CK |
| Broche 37 | PB13 — GPIO, SPI2_SCK, USART3_CTS |
| Broche 38 | PB14 — GPIO, SPI2_MISO, TIM12_CH1 |
| Broche 39 | PB15 — GPIO, SPI2_MOSI, TIM12_CH2 |
| Broche 40 | PA8 — GPIO, RCC_MCO_1, USART1_CK |
| Broche 41 | PA9 — GPIO, USART1_TX, CAN1_TX |
| Broche 42 | PA10 — GPIO, USART1_RX, CAN1_RX |
| Broche 43 | PA11 — GPIO, OTG_FS_DM, CAN1_TX |
| Broche 44 | PA12 — GPIO, OTG_FS_DP, CAN1_RX |
| Broche 45 | PA13 — JTMS/SWDIO |
| Broche 46 | VCAP — VCORE decoupling (internal SMPS output) |
| Broche 47 | VSS — Ground reference |
| Broche 48 | VDD — Main I/O supply |
| Broche 49 | PA14 — JTCK/SWCLK |
| Broche 50 | PA15 — JTDI, GPIO |
| Broche 51 | PC10 — GPIO, UART4_TX, SPI3_SCK |
| Broche 52 | PC11 — GPIO, UART4_RX, SPI3_MISO |
| Broche 53 | PC12 — GPIO, UART5_TX, SPI3_MOSI |
| Broche 54 | PD0 — GPIO, FMC_D2, CAN1_RX |
| Broche 55 | PD1 — GPIO, FMC_D3, CAN1_TX |
| Broche 56 | PD2 — GPIO, UART5_RX, SDMMC1_CMD |
| Broche 57 | PD3 — GPIO, FMC_CLK |
| Broche 58 | PD4 — GPIO, USART2_RTS, FMC_NOE |
| Broche 59 | PD5 — GPIO, USART2_TX |
| Broche 60 | VSS — Ground reference |
| Broche 61 | VDD — Main I/O supply |
| Broche 62 | PD6 — GPIO, SAI1_D1, FMC_NWAIT |
| Broche 63 | PG9 — GPIO, USART6_RX, FMC_NE2 |
| Broche 64 | PG10 — GPIO, USART6_TX, FMC_NE3 |
| Broche 65 | PG11 — GPIO, FMC_A24 |
| Broche 66 | PG12 — GPIO, FMC_NE4, SPI6_MISO |
| Broche 67 | PG13 — GPIO, SPI6_SCK |
| Broche 68 | PG14 — GPIO, SPI6_MOSI |
| Broche 69 | VSS — Ground reference |
| Broche 70 | VDD — Main I/O supply |
| Broche 71 | PG15 — GPIO, FMC_NCAS |
| Broche 72 | PB3 — JTDO/TRACESWO, GPIO |
| Broche 73 | PB4 — NJRST, GPIO |
| Broche 74 | PB5 — GPIO, I2C1_SMBA |
| Broche 75 | PB6 — GPIO, I2C1_SCL, USART1_TX |
| Broche 76 | PB7 — GPIO, I2C1_SDA, USART1_RX |
| Broche 77 | PB8 — GPIO, I2C1_SCL, CAN1_TX |
| Broche 78 | PB9 — GPIO, I2C1_SDA, CAN1_RX |
| Broche 79 | PE7 — GPIO, TIM1_ETR |
| Broche 80 | PE8 — GPIO, TIM1_CH1N |
| Broche 81 | PE9 — GPIO, TIM1_CH1 |
| Broche 82 | VSS — Ground reference |
| Broche 83 | VDD — Main I/O supply |
| Broche 84 | PE10 — GPIO, TIM1_CH2N |
| Broche 85 | PE11 — GPIO, TIM1_CH2 |
| Broche 86 | PE12 — GPIO, TIM1_CH3N |
| Broche 87 | PE13 — GPIO, TIM1_CH3 |
| Broche 88 | PE14 — GPIO, TIM1_CH4 |
| Broche 89 | PE15 — GPIO, TIM1_BKIN |
| Broche 90 | PB10 — Alternate function note: pin 90 is PB10-secondary; verify per package |
| Broche 91 | PD7 — GPIO, FMC_NCE2, USART2_CK |
| Broche 92 | PD8 — GPIO, FMC_D13, USART3_TX |
| Broche 93 | PD9 — GPIO, FMC_D14, USART3_RX |
| Broche 94 | PD10 — GPIO, FMC_D15, USART3_CK |
| Broche 95 | PD11 — GPIO, FMC_A16, USART3_CTS |
| Broche 96 | PD12 — GPIO, FMC_A17, TIM4_CH1 |
| Broche 97 | PD13 — GPIO, FMC_A18, TIM4_CH2 |
| Broche 98 | VSS — Ground reference |
| Broche 99 | VDD — Main I/O supply |
| Broche 100 | PD14 — GPIO, FMC_D0, TIM4_CH3 |
| Broche 101 | PD15 — GPIO, FMC_D1, TIM4_CH4 |
| Broche 102 | PG0 — GPIO, FMC_A10, ETH_MII_CRS_DV |
| Broche 103 | PG1 — GPIO, FMC_A11, ETH_MII_RXD2 |
| Broche 104 | PG2 — GPIO, FMC_A12, ETH_MII_RXD3 |
| Broche 105 | PG3 — GPIO, FMC_A13, ETH_MII_COL |
| Broche 106 | PG4 — GPIO, FMC_A14, ETH_MII_TX_EN |
| Broche 107 | PG5 — GPIO, FMC_A15, ETH_MII_RXD0 |
| Broche 108 | PG6 — GPIO, FMC_INT, ETH_MII_RXD1 |
| Broche 109 | PG7 — GPIO, FMC_INT2, ETH_MII_TXD2 |
| Broche 110 | PG8 — GPIO, ETH_PPS_OUT |
| Broche 111 | VSS — Ground reference |
| Broche 112 | VDD — Main I/O supply |
| Broche 113 | PC6 — GPIO, USART6_TX, TIM3_CH1 |
| Broche 114 | PC7 — GPIO, USART6_RX, TIM3_CH2 |
| Broche 115 | PC8 — GPIO, USART6_CK, TIM3_CH3 |
| Broche 116 | PC9 — GPIO, USART6_TX, TIM3_CH4 |
| Broche 117 | PA0 — Note: 117 shares Alt with pin 13 - verify per datasheet |
| Broche 118 | PA1 — Note: 118 shares Alt with pin 14 - verify per datasheet |
| Broche 119 | VSS — Ground reference |
| Broche 120 | VDD — Main I/O supply |
| Broche 121 | PA2 — Note: 121 shares Alt with pin 15 - verify per datasheet |
| Broche 122 | PA3 — Note: 122 shares Alt with pin 16 - verify per datasheet |
| Broche 123 | PA4 — Note: 123 shares Alt with pin 19 - verify per datasheet |
| Broche 124 | PA5 — Note: 124 shares Alt with pin 20 - verify per datasheet |
| Broche 125 | PA6 — Note: 125 shares Alt with pin 21 - verify per datasheet |
| Broche 126 | PA7 — Note: 126 shares Alt with pin 22 - verify per datasheet |
| Broche 127 | PC4 — Note: 127 shares Alt with pin 23 - verify per datasheet |
| Broche 128 | PC5 — Note: 128 shares Alt with pin 24 - verify per datasheet |
| Broche 129 | PB0 — Note: 129 shares Alt with pin 25 - verify per datasheet |
| Broche 130 | PB1 — Note: 130 shares Alt with pin 26 - verify per datasheet |
| Broche 131 | PB2 — Note: 131 shares Alt with pin 27 - verify per datasheet |
| Broche 132 | PF11 — Note: 132 shares Alt with pin 28 - verify per datasheet |
| Broche 133 | PF12 — Note: 133 shares Alt with pin 29 - verify per datasheet |
| Broche 134 | VSS — Ground reference |
| Broche 135 | VDD — Main I/O supply |
| Broche 136 | PB10 — Note: see pin 32 - ball grid repeat per datasheet |
| Broche 137 | PB11 — Note: see pin 33 |
| Broche 138 | VREF- — ADC negative reference (ground reference) |
| Broche 139 | PA8 — Note: 139 shares Alt with pin 40 - verify per datasheet |
| Broche 140 | PA9 — Note: 140 shares Alt with pin 41 - verify per datasheet |
| Broche 141 | PA10 — Note: 141 shares Alt with pin 42 - verify per datasheet |
| Broche 142 | PA11 — Note: 142 shares Alt with pin 43 - verify per datasheet |
| Broche 143 | PA12 — Note: 143 shares Alt with pin 44 - verify per datasheet |
| Broche 144 | NC — Not connected (per datasheet) |
Applications typiques
STM32H745ZGT6 convient pour 7 applications: Industrial Motor Control (FOC / PMSM / BLDC), Audio DSP and Class-D Amplifier Controllers, Human-Machine Interface (TFT-LCD + Touch), IoT Edge Gateway and Industrial Connectivity, Programmable Logic Controller (PLC) and Building Automation, Medical Instrumentation and Patient Monitoring, High-End Power Supply and Digital SMPS Control.
Industrial Motor Control (FOC / PMSM / BLDC)
The STM32H745ZGT6's dual-core architecture maps perfectly onto field-oriented control inverters: the Cortex-M7 at 480 MHz executes the inner current loop with single-cycle math and FFT-grade DSP instructions, while the Cortex-M4 at 240 MHz handles CAN FD state machines and protective diagnostics. Its HRTIM (high-resolution timer) supports sub-100 ns PWM edge placement needed for SiC and GaN gate drivers, and the 16-bit ADC enables synchronized current-sensing at sub-microsecond jitter. The integrated SMPS reduces BOM by generating the VCORE rail from a single 3.3 V supply, and the LQFP-144 footprint exposes all three HRTIM outputs plus abundant GPIO for encoder and resolver interfaces.
Recommandé
Audio DSP and Class-D Amplifier Controllers
In pro-audio amplifiers and effects processors, the M7 core runs audio DSP pipelines - biquad filters, limiters, FFT analysis - while the M4 manages SAI/I2S stream routing and front-panel UI without blocking DSP. The dual-core ensures 24-bit / 96 kHz audio does not glitch under UI load. DMA2D and the Chrom-ART accelerator offload graphics onto touch-panel feedback, and the SAI peripherals support up to four stereo pairs with TDM. Audio designers benefit from deterministic latency because the M4 can service SAI under interrupts while the M7 runs the audio engine at lower priority.
Recommandé
Human-Machine Interface (TFT-LCD + Touch)
HMI panels running 480x272 or 800x480 RGB displays lean on the M7's LTDC/Chrom-ART engine to redraw widgets at 60 Hz without CPU stalls. The M4 simultaneously scans touch controllers over I2C and handles USB-CDC communication to a host PLC, partitioning concerns cleanly. The LQFP-144 package exposes up to 88 GPIO - sufficient for parallel RGB888 plus touch and keypad without a serial-display penalty. Framebuffer in the 1 MB SRAM avoids external SDRAM for moderate UIs, cutting the BOM.
Recommandé
IoT Edge Gateway and Industrial Connectivity
Industrial IoT gateways aggregate sensor data over RS-485, CAN FD, and Modbus TCP, then publish to the cloud over Ethernet or LTE. The M4 handles real-time fieldbus protocols deterministically, while the M7 runs TLS/DTLS cryptographic stacks, JSON parsing, and MQTT clients at high throughput. The Ethernet MAC with TSN support on the H745 enables time-sensitive networking requirements emerging in Industry 4.0 deployments. Hardware AES/RNG accelerators offload TLS handshakes, and 1 MB Flash accommodates full TLS stacks plus application code without external QSPI.
Recommandé
Programmable Logic Controller (PLC) and Building Automation
PLC scan cycles require deterministic millisecond timing - perfect for the M4 running IEC 61131-3 POU execution on deterministic tick rates. The M7 crunches higher-level analytics, real-time dashboards, or analytics on energy metering ADCs. The 144-pin LQFP offers enough GPIO for relay drivers, isolated digital inputs, and analog channels; the 16-bit ADC resolves below 1 mV for energy metering CT/PT inputs. Building automation clusters (BACnet, KNX, Modbus) all benefit from isolated CAN FD communications.
Recommandé
Medical Instrumentation and Patient Monitoring
Patient monitors isolate safety-critical ECG/signal sampling on the M4 under tight interrupts, while the M7 handles graphical display rendering and trend analysis using DSP filters. The STM32H745 IEC 60730 / IEC 60335 software-test-library support accelerates functional-safety certification for home healthcare devices. Hardware 16-bit ADC and DAC simplify analog signal chains for ECG front-ends, and the on-chip crypto and unique-ID support tamper-detection requirements for FDA submission documentation.
Recommandé
High-End Power Supply and Digital SMPS Control
Digital-controlled telecom-grade power supplies use high-resolution PWM from the HRTIM (217 ps resolution) to drive PFC plus LLC topologies with sub-1% output accuracy. The M7 manages the closed-loop digital control loop while the M4 oversees telemetry, PMBus, and brownout protection. The integrated step-down SMPS can be repurposed for housekeeping rails; if higher current is needed, the SMPS is bypassed and an external buck feeds VCORE directly. The part's dual-rail analog comparators enable sub-cycle overcurrent protection.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour STM32H745ZGT6 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | STM32H745IIT6 | STM32H745IIK6 | STM32H730IBK6Q |
|---|---|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Package | LQFP-144 (20x20) | LQFP-176 - different package | UFBGA-176 - different package | UFBGA-176 - different package |
| Core Architecture | Dual Cortex-M7 + Cortex-M4 | Dual Cortex-M7 + Cortex-M4 | Dual Cortex-M7 + Cortex-M4 | Single Cortex-M7 |
| M7 Max Clock | 480 MHz | 480 MHz | 480 MHz | 550 MHz |
| M4 Max Clock | 240 MHz | 240 MHz | 240 MHz | N/A (no M4) |
| Flash Memory | 1 MB | 2 MB (+100%) | 2 MB (+100%) | 1 MB (same) |
| SRAM | ~1 MB | ~1 MB | ~1 MB | ~564 KB |
| Internal SMPS | Yes | Yes | Yes | Yes |
| Automotive Grade Option | Industrial | Industrial (Q suffix for Q1) | Industrial | AEC-Q100 grade 2 (Q suffix) |
Principaux différenciateurs
- Dual-core asymmetric M7+M4 architecture on the same package (vs STM32H730IBK6Q)
- Larger Flash than single-bank counterparts (vs STM32H745ZIT6 (2 MB variant))
- Industrial LQFP-144 form factor with abundant GPIO (vs BGA-package STM32H745IIK6)
Notes de conception
The STM32H745ZGT6 integrates a step-down SMPS that converts the 1.62-3.6 V VDD rail to the VCORE domain. Per the datasheet, place a 4.7 uH power inductor and 4.7 uF X7R output capacitor within 5 mm of the VCAP pin, plus a 100 nF high-frequency decoupling capacitor. Estimated: at 480 MHz the M7 core draws ~100 mA from VCORE, and the M4 adds ~25 mA; an external LDO may still be required if you need analog supply isolation for the ADC VREF+ rail.
While the LQFP-144 has no exposed pad, the package thermal resistance is around 35-45 C/W (theta_JA) on a 2-layer JEDEC test board - using a 4-layer board with continuous inner ground planes drops theta_JA below 25 C/W. At 480 MHz on the M7 plus a loaded M4 the package can dissipate 0.7-1.0 W in typical firmware; in industrial environments with no airflow, ensure the layout has thermal vias under the central pad area if present in your variant.
Each VDD pin should have a 100 nF decoupling capacitor placed within 2 mm of the pin, plus a 4.7 uF bulk capacitor near the package. LQFP-144 lead length and inductance are non-negligible at 480 MHz I/O toggling rates - keep clock traces short and impedance-controlled. SMPS inductor traces should be kept narrow to minimize radiated EMI, but its ground return should be wide and contiguous.
Do not assume the dual cores share the same toolchain projects - they require separate linker scripts and start-up code via STM32CubeIDE or STM32CubeMX. The OpenAMP library enables inter-core messaging; without it the cores cannot share resources safely. Boot pinning (BOOT0/BOOT1) selects which core starts first; verify your bank configuration before flashing. Also, the VCORE domain cannot be directly probed with multimeter without risking damage - use STM32CubeIDE's debug register view.
High-speed QSPI to external NOR flash or PSRAM should be length-matched within 50 mil on each lane to maintain timing at 200+ MHz SDR/DDR. Ethernet RMII traces should be 50 ohm controlled-impedance and routed away from SMPS switching nodes. Place the 25 MHz HSE crystal within 5 mm of OSC_IN/OSC_OUT pins, guarded by a continuous ground ring, and tie both crystal load capacitors to the same reference ground as the MCU.
Informations de conformité
ECOPACK2 environmental compliance per STMicroelectronics datasheet. Industrial grade (-40C to +85C); not AEC-Q100 qualified - select ZIT6Q/GTK6Q for automotive.
