TPS543C20RVFR - 40A 14V Sync Step-Down SWIFT Converter | TI
Référence : TPS543C20RVFR ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $6.85 | $6,85 |
| 10 | $6.17 | $61,70 |
| 100 | $5.48 | $548,00 |
| 500 | $4.93 | $2 465,00 |
| 1 000 | $4.38 | $4 380,00 |
TPS543C20RVFR Présentation
A buck (step-down) DC-DC switching regulator is a power-management integrated circuit that converts a higher DC input voltage into a lower DC output voltage by rapidly switching an internal MOSFET pair and smoothing the resulting pulsed waveform with an LC output filter. Within the broader power-electronics taxonomy, the TPS543C20 sits in the non-isolated POL (point-of-load) converter family -> DC-DC switching regulator -> voltage regulator -> power-management IC hierarchy. SWIFT converters from TI combine internal MOSFETs, current-mode control, and adaptive compensation to deliver high efficiency at multi-MHz switching frequencies in compact surface-mount footprints.
Key features include integrated 3 mΩ/0.9 mΩ stacked NexFET power stages, differential remote sensing for tight load-point regulation, monolithic integration that eliminates external compensation components, and a stackable architecture that lets two devices operate in parallel for up to 80 A. Internally compensated emulated peak current-mode control provides a wide bandwidth loop, and the switching frequency is synchronizable to an external clock for EMI-sensitive rails. A built-in integrator and ramp-tracking amplifier allow stable operation across the full 0.6 V to 5.5 V output range.
The TPS543C20 architecture uses internal MOSFETs driven by an emulated peak current-mode controller with a clock-synchronizable, fixed-frequency modulator. The internal integrator and directly amplifying ramp tracking loop eliminate the need for external compensation across the wide operating range, simplifying PCB layout and shrinking the BOM. Differential sensing cancels PCB IR-drop in high-current paths, allowing the regulated voltage at the load to remain within ±1% tolerance even at 40 A.
Typical applications include space-constrained point-of-load rails in networking switches and routers, FPGA/ASIC core and transceiver supplies, server and storage POLs, and stacked 80 A configurations for high-current ASIC and processor rails. The 40-pin PowerLFQFN package exposes the die through a thermal pad, allowing multi-layer PCB copper pours to dissipate the heat generated at full load.
When designing with the TPS543C20, observe the datasheet-required minimum input/output capacitor values (including ripple-current-rated ceramics) and keep the SYNC/FSEL loop short to the IC. Differential remote-sense traces must be routed as a matched pair directly to the load to suppress PCB IR-drop in high-current applications.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Alternatives de remplacement direct pour TPS543C20RVFR — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec TPS543C20RVFR (même facteur de forme et même empreinte) — différant par Clock Synchronization, Control Mode, Input Voltage Range, Output Voltage Range, Package.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
TPS543C20ARVFR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
TPS543C20RVFT
✅ Remplacement direct✓ En stock
$7.1 / unité
Voir la fiche technique →TPS543C20ARVFT
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
TPS543B20RVFR
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
TPS543C20RVFR
✅ Remplacement direct✓ En stock
$4.38 / unité
Voir la fiche technique →TPS543C20RVFR Valeurs maximales et caractéristiques électriques
| Topologie | Synchronous Buck (Step-Down) |
| Plage de tension d'entrée | 4 V to 14 V (A-version: 4 V to 16 V) |
| Plage de tension de sortie | 0.6 V to 5.5 V |
| Courant de sortie maximal | 40 A continuous |
| Control Mode | Emulated Peak Current Mode |
| Internal MOSFETs (High-Side / Low-Side) | 3 mΩ / 0.9 mΩ stacked NexFET |
| Type de sortie | Adjustable (resistor divider) |
| Remote Sensing | Differential (true remote sense) |
| Clock Synchronization | Yes (SYNC input) |
| Compensation | Adaptive Internal (no external comp network) |
| Boîtier | 40-Pin PowerLFQFN (RVF) with exposed thermal pad |
| Type de montage | Surface Mount |
| Température de fonctionnement | -40C to +125C junction |
| Statut RoHS | Compliant |
Configuration des broches de TPS543C20RVFR
| Broche 1 | VIN — Input voltage supply |
| Broche 2 | VIN — Input voltage supply |
| Broche 3 | PGND — Power ground |
| Broche 4 | SW — Switching node |
| Broche 5 | SW — Switching node |
| Broche 6 | SW — Switching node |
| Broche 7 | SW — Switching node |
| Broche 8 | PGND — Power ground |
| Broche 9 | BOOT — Bootstrap capacitor for high-side gate drive |
| Broche 10 | VOUT — Output voltage sense |
| Broche 11 | VOUT — Output voltage sense |
| Broche 12 | PGND — Power ground |
| Broche 13 | PGND — Power ground |
| Broche 14 | PGND — Power ground |
| Broche 15 | PGND — Power ground |
| Broche 16 | AGND — Analog ground |
| Broche 17 | DIFF+ — Differential remote sense positive |
| Broche 18 | DIFF- — Differential remote sense negative |
| Broche 19 | FBK — Feedback input |
| Broche 20 | REF — Reference voltage output |
| Broche 21 | EN — Enable input |
| Broche 22 | PGOOD — Power-good indicator output |
| Broche 23 | SYNC — External clock synchronization input |
| Broche 24 | FSEL — Frequency select resistor input |
| Broche 25 | MODE — Mode selection (stack primary/secondary) |
| Broche 26 | PWM/STACK — PWM output / stack interface |
| Broche 27 | TRK — Tracking input |
| Broche 28 | SS — Soft-start capacitor |
| Broche 29 | COMP — Compensation node (internal) |
| Broche 30 | AVIN — Analog input supply |
| Broche 31 | PGND — Power ground |
| Broche 32 | PGND — Power ground |
| Broche 33 | PGND — Power ground |
| Broche 34 | PGND — Power ground |
| Broche 35 | VIN — Input voltage supply |
| Broche 36 | VIN — Input voltage supply |
| Broche 37 | VIN — Input voltage supply |
| Broche 38 | VIN — Input voltage supply |
| Broche 39 | VIN — Input voltage supply |
| Broche 40 | NC — Not connected (per datasheet) |
| Broche EP | PGND_PAD — Exposed thermal pad - power ground |
Applications typiques
TPS543C20RVFR convient pour 6 applications: FPGA Core and Transceiver POL Supply, Networking Switch and Router ASIC Rails, Server and Storage Point-of-Load Conversion, Stacked 80 A High-Current ASIC Rail, Industrial 24 V to 5 V / 3.3 V Conversion, PCIe Card Auxiliary Power Rails.
FPGA Core and Transceiver POL Supply
The TPS543C20RVFR delivers 0.85 V to 1.8 V rails at up to 40 A directly to high-performance FPGAs (Xilinx Versal, Intel Stratix, etc.). Its 0.6 V to 5.5 V adjustable output covers every common FPGA core and transceiver voltage. Differential remote sensing maintains ±1% regulation at the load by canceling PCB IR-drop in the 40 A power path. Adaptive internal compensation eliminates the comp network that typically clutters dense FPGA power trees, shrinking the POL footprint.
Recommandé
Networking Switch and Router ASIC Rails
Routers and top-of-rack switches require multiple 40 A to 80 A rails for switch ASICs and packet processors. The TPS543C20RVFR handles one rail at 40 A, and two devices stack for 80 A on the most demanding ASIC rails. The SYNC input lets multiple TPS543C20 phases lock to a single clock, eliminating beat-frequency noise in dense multi-rail enclosures. The 4 V to 14 V input accepts standard 12 V backplane/connector power directly.
Recommandé
Server and Storage Point-of-Load Conversion
Inside hyperscale servers, 12 V main bus power is stepped down at the motherboard to 0.6 V to 3.3 V for CPUs, DDR5, and accelerators. The TPS543C20RVFR fits this POL slot with 95% peak efficiency, programmable frequency, and remote sensing. The 40-pin PowerLFQFN footprint allows high-density placement next to memory DIMMs and M.2 SSDs. Stackable architecture scales to 80 A for accelerator cards without paralleling external MOSFETs.
Recommandé
Stacked 80 A High-Current ASIC Rail
Two TPS543C20RVFR devices in a primary-secondary stack deliver 80 A continuous to a single high-current ASIC rail, per the TI reference design. Internal current-sharing loop balances load automatically without external circuitry. This eliminates discrete parallel-FET designs that require complex current-matching networks. Differential sensing on both phases keeps the load-point regulation within ±1% even with 80 A of PCB IR-drop.
Recommandé
Industrial 24 V to 5 V / 3.3 V Conversion
The TPS543C20A revision (4 V to 16 V input) tolerates industrial 24 V rails when paired with a TVS/clamp pre-protector. Its 40 A capability drives motor-control, PLC logic, and industrial Ethernet PHYs at 5 V or 3.3 V. The exposed thermal pad of the PowerLFQFN package couples directly to PCB copper for fan-less cooling in sealed enclosures. Differential sensing compensates for long harness drops in distributed control cabinets.
Recommandé
PCIe Card Auxiliary Power Rails
PCIe accelerator cards draw auxiliary 12 V from the edge connector and step down to 0.8 V to 1.2 V for the local ASIC. The TPS543C20RVFR fits this application with 40 A capability, 12 V input direct from the slot, and a compact 40-pin PowerLFQFN footprint that fits inside tight add-in-card height envelopes. Programmable soft-start lets the card meet PCIe hot-plug inrush limits without extra hot-swap controllers.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour TPS543C20RVFR — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | TPS543C20ARVFR | TPS543C20RVFT | TPS543C20ARVFT | TPS543B20RVFR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 40-Pin PowerLFQFN (RVF) | 40-Pin PowerLFQFN (RVF) - same | 40-Pin PowerLFQFN (RVF) - same | 40-Pin PowerLFQFN (RVF) - same | 40-Pin PowerLFQFN (RVF) - same |
| Input Voltage Range | 4 V to 14 V | 4 V to 16 V | 4 V to 14 V | 4 V to 16 V | 4 V to 14 V |
| AEC-Q100 Automotive Qualified | No | No | No | No | No |
| RoHS / Lead-Free | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes | Yes / Yes |
Principaux différenciateurs
- Highest power density in 40-pin PowerLFQFN at 40 A (vs TPS543B20RVFR)
- Wider input voltage range with the A-version (vs TPS543C20RVFR (standard))
- True stackable architecture for 80 A (vs TPS543C20RVFT (single phase))
Notes de conception
Estimated: At VIN=12V, VOUT=1.0V, 40A load, the TPS543C20RVFR dissipates approximately 12 V x 40 A x (1 - 0.95) = 24 W (assuming 95% efficiency). The 40-pin PowerLFQFN package couples this heat through its exposed thermal pad to PCB copper. Per TI TPS543C20 datasheet, designers should use a minimum 6-layer board with at least 1 oz copper on inner layers and a 2 oz top layer to keep junction temperature below 125C. A thermal pad land with at least 25 thermal vias into the inner copper pour is mandatory.
Differential remote sense traces (DIFF+ and DIFF-) must be routed as a matched-length, tightly-coupled pair directly from the IC pins to the load sense points, per TI TPS543C20 datasheet layout guidelines. This cancels common-mode noise from the switching node and prevents ground loops. Place the SYNC and FSEL traces away from the SW node to avoid capacitive coupling; if possible, shield them with a ground trace. Keep input/output ceramic capacitors (X7R, ripple-current rated) within 2 mm of the IC pins.
Do not exceed the absolute maximum input voltage of 18 V on the TPS543C20 (14 V version) or 20 V on the TPS543C20A (16 V version) per the TI datasheet. The TPS548D21RVFT is NOT pin-compatible with the TPS543C20 - per the TI E2E forum, switching between them requires redesign of both schematic and PCB layout. When stacking two devices for 80 A, follow the TI TPS543C20 reference design exactly to ensure the primary/secondary current-sharing loop remains stable across all load steps.
Keep the SW (switching) node copper area small to minimize radiated EMI. Use a shielded inductor (semi-toroidal) at the output rather than an open drum core to reduce near-field emissions. The exposed thermal pad (EP) must be soldered to a sufficiently large copper pour (per datasheet minimum) to keep thermal resistance within the spec. Star-ground the analog GND (AGND) returns into the PGND at a single point to avoid ground bounce corrupting the feedback loop.
Informations de conformité
RoHS compliant and lead-free per TI product page. Halogen-free and full material declaration available via TI MDDS download. Not AEC-Q100 qualified - for automotive designs use the TPS543C20-Q1 variants. For full SVHC REACH declaration see ti.com/product/TPS543C20.
