EP2S60F1020C4N vs EP2S60F1020I4 השוואה
השוואה מפורטת זה לצד זה של EP2S60F1020C4N מאת Intel ו EP2S60F1020I4 מאת Altera. השווה מפרטים עיקריים, פרמטרים חשמליים, אריזה, סטטוס מחזור חיים, תמחור וזמינות כדי לקבוע את הרכיב הטוב ביותר לדרישות העיצוב שלך.
השוואת מפרטים
| פרמטר | EP2S60F1020C4N | EP2S60F1020I4 |
|---|---|---|
| מותג | Intel | Altera |
| קטגוריה | FPGA & CPLD | FPGA & CPLD |
| סטטוס מחזור חיים | Obsolete | NRND |
| Series | Stratix II | Stratix II |
| Family | Stratix II (EP2S60) | — |
| Logic Elements | 60,440 | — |
| Adaptive Logic Modules (ALMs) | 30,220 (approx.) | — |
| Logic Array Blocks (LABs) | 3,022 | — |
| Embedded Memory (bits) | 2,544,192 | 2,544,192 |
| Embedded Memory Blocks | M512/M4K/M-RAM TriMatrix memory | — |
| DSP Blocks (18-bit x 18-bit) | Up to 48 (24 per DSP block column pair typical) | — |
| User I/Os | 718 | — |
| Maximum Core Frequency | 711.24 MHz (per Arrow listing) | — |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| מארז | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) | — |
| סוג הרכבה | Surface Mount (BGA) | Surface Mount |
| Operating Temperature Grade | Commercial (C4 suffix indicates commercial, speed grade 4) | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | — |
| PLLs / Clock Networks | Yes - on-chip PLLs and global clock networks | — |
| סטטוס RoHS | EU RoHS compliant with exemption (per Arrow listing) | Non-compliant (contains lead per legacy Altera package) |
| Manufacturer | — | Intel / Altera |
| Logic Elements (LEs) | — | 60,440 |
| Number of LABs/CLBs | — | 3022 |
| Number of CLBs | — | 24176 |
| Maximum User I/O | — | 718 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Operating Voltage (Core) | — | 1.2 V |
| Temperature Grade | — | Industrial (-40C to +100C TJ) |
| Package Type | — | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Package Dimensions | — | 33 mm x 33 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Number of PLLs | — | 12 |
| Global Clock Networks | — | 16 |
| Embedded Multipliers (18x18) | — | 36 |
| Transceiver Count | — | 0 (no embedded transceivers) |
| Maximum Embedded Memory Bandwidth | — | [DATA_NEEDED: memory bandwidth spec] |