RTAX250SL-1LG624V vs RTAX250SL-1CG624E השוואה
השוואה מפורטת זה לצד זה של RTAX250SL-1LG624V מאת Microchip Technology ו RTAX250SL-1CG624E מאת Microchip Technology. השווה מפרטים עיקריים, פרמטרים חשמליים, אריזה, סטטוס מחזור חיים, תמחור וזמינות כדי לקבוע את הרכיב הטוב ביותר לדרישות העיצוב שלך.
Microchip Technology
RTAX250SL-1LG624V - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-1LG624V ✓ פעילMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ פעילהשוואת מפרטים
| פרמטר | RTAX250SL-1LG624V | RTAX250SL-1CG624E |
|---|---|---|
| מותג | Microchip Technology | Microchip Technology |
| קטגוריה | FPGA & CPLD | FPGA & CPLD |
| סטטוס מחזור חיים | פעיל | פעיל |
| Equivalent System Gates | 250,000 gates | 250,000 gates |
| Logic Cells | 4224 | 4224 |
| Configurable Logic Blocks (CLBs) | 2816 | 2816 |
| Architecture | CMOS antifuse (Axcelerator-derived) | — |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Core Supply Voltage | 1.5 V nominal | 1.5 V (1.425 V to 1.575 V) |
| Speed Grade | -1 | — |
| מארז | 624-terminal ceramic CGA (LG624), 1.270 mm terminal pitch | 624-ball Ceramic Column Grid Array (CCGA-624) |
| סוג הרכבה | Surface Mount | Surface Mount (ceramic column grid array) |
| טמפרטורת פעולה | -55C to +125C | -55C to +125C |
| Configuration Type | One-Time Programmable (antifuse) | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clock Resources | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Dedicated carry logic | — |
| Application Domain | Space-flight systems | — |
| סטטוס RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Total Ionizing Dose Tolerance | [DATA_NEEDED: TID level] | — |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Process Technology | — | 0.15 um CMOS |
| Logic Family | — | CMOS |
| Radiation Tolerance | — | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |