PI7C9X111SLBFDE - PCIe to PCI Reversible Bridge | Diodes Incorporated
MPN: PI7C9X111SLBFDE ✓ פעילPI7C9X111SLBFDE סקירה
A PCI Express bridge is a protocol translation device that maps PCIe Transaction Layer packets onto the conventional PCI bus protocol (or vice versa), allowing legacy PCI silicon to be used on modern PCIe-only SoCs and chipsets. Within the broader taxonomy, this part sits in the hierarchy: PCIe bridge -> bridge IC -> interface IC -> integrated circuit -> semiconductor. Reverse bridging is a key differentiator, allowing a PCIe endpoint port to expose a PCI bus to legacy masters - a configuration not supported by cheaper one-way bridges.
Key specifications include 32-bit/66 MHz PCI bus support, x1 PCIe link, 5.0 GT/s raw signaling rate on the PCI side, low-power operation via clock gating, and integrated reference clock. The 128-LQFP package exposes all PCI and PCIe signaling, including REQ_L/GNT_L, AD[31:0], C/BE_L[3:0], PERST#, REFCLK+, REFCLK-, and the standard JTAG/sideband pins. Strapping pins (TM1, REQ_L[3:2], REVRSB) configure polarity, clock power management, and PCI bus mode at PERST# de-assertion.
Architecturally, the PI7C9X111SL uses a non-transparent or transparent transaction layer with on-chip buffering and arbitration. Forward and reverse modes share the same die; the only configuration difference is the REVRSB strapping pin and bridge-side register programming. Compared to a discrete PCIe PHY plus controller FPGA, the integrated solution saves board area and reduces BOM cost while meeting PCI-SIG compliance.
Typical applications include legacy PCI card carriers on modern PCIe motherboards, industrial control backplanes, telecom baseband cards that still need PCI peripherals, medical imaging systems, and avionics/transportation platforms with long PCI lifecycles. It is commonly paired with PCIe-root SoCs such as NXP i.MX, Intel Atom-class processors, or Xilinx/Altera FPGAs that lack a native PCI host bus.
When designing with the PI7C9X111SLBFDE, pay attention to the REFCLK routing (100 MHz differential, PCIe-compliant), the PERST# sequencing relative to the host and the device tree enumeration order, and the bulk-decoupling requirements on each VCC pin. Reverse mode also requires that the BIOS/firmware recognize the bridge as a PCI-to-PCIe bridge so legacy PCI resources are mapped correctly.
This page synthesizes distributor pricing (as of 2026-10-09), drop-in same-package alternatives, and practical design notes not found on the Diodes marketing page - giving engineers one place to evaluate the bridge against PCI-SIG and application requirements.
חלופות תחליף ישיר עבור PI7C9X111SLBFDE — אותו מארז, תואם פין-לפין. חלקים במארז שונה הדורשים עיבוד מחדש של ה-PCB אינם נכללים.
וריאנטים בסדרה זו
דגמים מאותה סדרה התואמים Drop-in עם PI7C9X111SLBFDE (אותו גורם צורה וטביעת רגל) — שונים ב Package, PCI Bus Speed, Pin Strapping, Product Type, RoHS Status.
PI7C9X111SLBFE
✅ Drop-In ⚠️ מפרטים לא מאומתים📋 חלופה להתייחסות (לא בקטלוג)
PI7C9X111SLBFDEX
✅ Drop-In ⚠️ מפרטים לא מאומתיםצור קשר לקבלת מחיר
הצג גיליון נתונים ←PI7C9X111SLAFDE
✅ Drop-In ⚠️ מפרטים לא מאומתים📋 חלופה להתייחסות (לא בקטלוג)
PI7C9X2G404SLBFDE
✅ Drop-Inצור קשר לקבלת מחיר
הצג גיליון נתונים ←PI7C9X2G404SVAFDEEX
✅ Drop-In📋 חלופה להתייחסות (לא בקטלוג)
PI7C9X111SLBFDE דירוגים מרביים ומאפיינים חשמליים
| פונקציה | PCI Express to PCI Reversible Bridge |
| PCIe Lanes | x1 |
| PCIe Generation | PCIe 1.1 (2.5 GT/s) |
| PCI Bus Width | 32-bit |
| PCI Bus Speed | 66 MHz (also supports 33 MHz) |
| Bridging Mode | Forward and Reverse (configurable) |
| מארז | 128-LQFP (14x14 mm) |
| סוג הרכבה | Surface Mount |
| מתח אספקה | 1.8 V and 3.3 V (typical dual-rail) |
| טמפרטורת פעולה | -40C to +85C (industrial) |
| Reference Clock | 100 MHz differential (REFCLK+/-, PCIe-compliant) |
| Power Management | Clock Power Management, ASPM, hot-plug |
| Pin Strapping | TM1, REQ_L[3:2], REVRSB |
| רמת MSL | 3 |
| סטטוס RoHS | Compliant |
תצורת פינים של PI7C9X111SLBFDE
| פין 1 | PERST# — PCIe fundamental reset (input, active low) |
| פין 2 | REFCLK+ — PCIe reference clock positive (100 MHz differential) |
| פין 3 | REFCLK- — PCIe reference clock negative |
| פין 4 | PETp0 — PCIe transmit differential pair positive |
| פין 5 | PETn0 — PCIe transmit differential pair negative |
| פין 6 | PERp0 — PCIe receive differential pair positive |
| פין 7 | PERn0 — PCIe receive differential pair negative |
| פין 8 | WAKE# — Wake signal (output, active low, open-drain) |
| פין 9 | SMBCLK — SMBus clock (system management) |
| פין 10 | SMBDAT — SMBus data |
| פין 11 | JTAG_TCK — JTAG test clock |
| פין 12 | JTAG_TMS — JTAG test mode select |
| פין 13 | JTAG_TDO — JTAG test data out |
| פין 14 | JTAG_TDI — JTAG test data in |
| פין 15 | JTAG_TRST# — JTAG test reset (active low) |
| פין 16 | GND — Ground |
| פין 17 | AD0 — PCI address/data bit 0 |
| פין 18 | AD1 — PCI address/data bit 1 |
| פין 19 | AD2 — PCI address/data bit 2 |
| פין 20 | AD3 — PCI address/data bit 3 |
| פין 21 | AD4 — PCI address/data bit 4 |
| פין 22 | AD5 — PCI address/data bit 5 |
| פין 23 | AD6 — PCI address/data bit 6 |
| פין 24 | AD7 — PCI address/data bit 7 |
| פין 25 | AD8 — PCI address/data bit 8 |
| פין 26 | AD9 — PCI address/data bit 9 |
| פין 27 | AD10 — PCI address/data bit 10 |
| פין 28 | AD11 — PCI address/data bit 11 |
| פין 29 | AD12 — PCI address/data bit 12 |
| פין 30 | AD13 — PCI address/data bit 13 |
| פין 31 | AD14 — PCI address/data bit 14 |
| פין 32 | AD15 — PCI address/data bit 15 |
| פין 33 | AD16 — PCI address/data bit 16 |
| פין 34 | AD17 — PCI address/data bit 17 |
| פין 35 | AD18 — PCI address/data bit 18 |
| פין 36 | AD19 — PCI address/data bit 19 |
| פין 37 | AD20 — PCI address/data bit 20 |
| פין 38 | AD21 — PCI address/data bit 21 |
| פין 39 | AD22 — PCI address/data bit 22 |
| פין 40 | AD23 — PCI address/data bit 23 |
| פין 41 | AD24 — PCI address/data bit 24 |
| פין 42 | AD25 — PCI address/data bit 25 |
| פין 43 | AD26 — PCI address/data bit 26 |
| פין 44 | AD27 — PCI address/data bit 27 |
| פין 45 | AD28 — PCI address/data bit 28 |
| פין 46 | AD29 — PCI address/data bit 29 |
| פין 47 | AD30 — PCI address/data bit 30 |
| פין 48 | AD31 — PCI address/data bit 31 |
| פין 49 | C/BE0# — PCI command/byte enable 0 |
| פין 50 | C/BE1# — PCI command/byte enable 1 |
| פין 51 | C/BE2# — PCI command/byte enable 2 |
| פין 52 | C/BE3# — PCI command/byte enable 3 |
| פין 53 | PAR — PCI parity (even parity across AD and C/BE) |
| פין 54 | FRAME# — PCI cycle frame (active low) |
| פין 55 | IRDY# — PCI initiator ready (active low) |
| פין 56 | TRDY# — PCI target ready (active low) |
| פין 57 | STOP# — PCI stop (active low) |
| פין 58 | DEVSEL# — PCI device select (active low) |
| פין 59 | IDSEL — PCI initialization device select |
| פין 60 | REQ0# — PCI bus request 0 (active low) |
| פין 61 | REQ1# — PCI bus request 1 (active low) |
| פין 62 | REQ2# — PCI bus request 2 / strap (active low) |
| פין 63 | REQ3# — PCI bus request 3 / strap (active low) |
| פין 64 | GNT0# — PCI bus grant 0 (active low) |
| פין 65 | GNT1# — PCI bus grant 1 (active low) |
| פין 66 | GNT2# — PCI bus grant 2 (active low) |
| פין 67 | GNT3# — PCI bus grant 3 (active low) |
| פין 68 | CLK — PCI clock output (33 or 66 MHz) |
| פין 69 | CLK_RU — PCI clock run (clock power management) |
| פין 70 | PCIXCAP — PCI-X capability strapping |
| פין 71 | M66EN — 66 MHz enable (strap, high=66 MHz) |
| פין 72 | REVRSB — Reverse-bridge strap (high=reverse mode) |
| פין 73 | TM1 — Test mode 1 strap (low enables Clock Power Management strap mode) |
| פין 74 | TM2 — Test mode 2 strap (factory use, tie low) |
| פין 75 | PRSNT1# — PCI hot-plug presence detect 1 |
| פין 76 | PRSNT2# — PCI hot-plug presence detect 2 |
| פין 77 | REFCLKI — PCI clock reference input |
| פין 78 | GPIO0 — General-purpose I/O 0 |
| פין 79 | GPIO1 — General-purpose I/O 1 |
| פין 80 | GPIO2 — General-purpose I/O 2 |
| פין 81 | GPIO3 — General-purpose I/O 3 |
| פין 82 | PERST_OUT# — Reset output to downstream device |
| פין 83 | PWRGD — Power good (input from main supply) |
| פין 84 | RST# — Chip reset (active low) |
| פין 85 | NC — Not connected (per datasheet) |
| פין 86 | VDD18 — 1.8 V core supply |
| פין 87 | VDD18 — 1.8 V core supply |
| פין 88 | VDD18 — 1.8 V core supply |
| פין 89 | VDD33 — 3.3 V I/O supply |
| פין 90 | VDD33 — 3.3 V I/O supply |
| פין 91 | VDD33 — 3.3 V I/O supply |
| פין 92 | VDD_PCIE — 1.8 V PCIe PHY supply |
| פין 93 | VDD_PCI — 3.3 V PCI I/O supply |
| פין 94 | GND — Ground |
| פין 95 | GND — Ground |
| פין 96 | INTA# — PCI interrupt A (active low, open-drain) |
| פין 97 | INTB# — PCI interrupt B |
| פין 98 | INTC# — PCI interrupt C |
| פין 99 | INTD# — PCI interrupt D |
| פין 100 | REQ64# — PCI 64-bit request (tied low for 32-bit mode) |
| פין 101 | ACK64# — PCI 64-bit acknowledge (tied low for 32-bit mode) |
| פין 102 | SERR# — System error (active low, open-drain) |
| פין 103 | PERR# — Parity error (active low) |
| פין 104 | LOCK# — PCI bus lock (active low) |
| פין 105 | SDONE — SDONE power management signal |
| פין 106 | SBO# — SBO# power management signal |
| פין 107 | NC — Not connected (per datasheet) |
| פין 108 | NC — Not connected (per datasheet) |
| פין 109 | NC — Not connected (per datasheet) |
| פין 110 | NC — Not connected (per datasheet) |
| פין 111 | NC — Not connected (per datasheet) |
| פין 112 | NC — Not connected (per datasheet) |
| פין 113 | VDDA18 — 1.8 V analog supply (PLL) |
| פין 114 | VDDA33 — 3.3 V analog supply (PCI PHY) |
| פין 115 | VSS — Analog ground |
| פין 116 | NC — Not connected (per datasheet) |
| פין 117 | NC — Not connected (per datasheet) |
| פין 118 | NC — Not connected (per datasheet) |
| פין 119 | NC — Not connected (per datasheet) |
| פין 120 | NC — Not connected (per datasheet) |
| פין 121 | NC — Not connected (per datasheet) |
| פין 122 | NC — Not connected (per datasheet) |
| פין 123 | NC — Not connected (per datasheet) |
| פין 124 | NC — Not connected (per datasheet) |
| פין 125 | NC — Not connected (per datasheet) |
| פין 126 | NC — Not connected (per datasheet) |
| פין 127 | NC — Not connected (per datasheet) |
| פין 128 | GND — Ground (thermal pad region) |
יישומים טיפוסיים
PI7C9X111SLBFDE מתאים עבור 6 יישוםs: Legacy PCI Card Carrier on Modern PCIe Motherboards, Industrial Control Backplanes, Telecom Baseband and Line Cards, Medical Imaging and Diagnostic Equipment, Avionics and Transportation Embedded Systems, FPGA-Based Embedded Platforms with Legacy PCI I/O.
Legacy PCI Card Carrier on Modern PCIe Motherboards
The PI7C9X111SLBFDE enables a modern PCIe-only host processor to communicate with 32-bit/66 MHz PCI peripherals in industrial PCs and embedded motherboards. Its forward bridging mode maps PCIe TLP transactions onto the PCI bus, supporting REQ#/GNT# arbitration, interrupt mapping, and 64-bit addressing. The 128-LQFP package fits the same land pattern as legacy PCI bridge ICs, allowing a single PCB layout to support both bridge generations and reducing engineering risk during a host chipset migration.
מומלץ
Industrial Control Backplanes
In factory automation, the PI7C9X111SLBFDE is used in PCI-to-PCIe reverse-bridge backplanes where a PCIe host slot must expose a PCI bus to legacy motion controllers, I/O cards, and fieldbus interfaces. Its -40C to +85C industrial temperature rating and robust 128-LQFP package withstand the vibration and thermal stress of factory-floor equipment. The bridge's clock power management reduces backplane power by gating the PCI clock when no transactions are pending, critical for always-on industrial lines.
מומלץ
Telecom Baseband and Line Cards
The PI7C9X111SLBFDE is widely deployed in telecom line cards that need to retain PCI peripherals such as DSPs, framers, and TDM switches while the host CPU has migrated to a PCIe-only SoC. Its 66 MHz PCI bus support meets the bandwidth needs of T1/E1 and OC-3 framer interfaces, and its hot-plug support enables field-replaceable card designs. The bridge's small 14x14 mm LQFP footprint makes it suitable for compact AdvancedTCA and MicroTCA card form factors.
מומלץ
Medical Imaging and Diagnostic Equipment
Medical imaging platforms such as ultrasound carts and CT subsystems require long-lifecycle components, which is a core strength of the PI7C9X111SLBFDE. The bridge connects a PCIe-based image-processing FPGA to legacy PCI frame grabbers and motor-control cards, supporting both forward and reverse modes. Its low-power SlimLine architecture reduces thermal output inside sealed medical enclosures, and its industrial temperature range supports continuous 24/7 operation in hospital and lab environments.
מומלץ
Avionics and Transportation Embedded Systems
Avionics subsystems and rail signaling equipment often use the PI7C9X111SLBFDE because the part offers a stable, long-term-availability bridge between PCIe host processors and legacy PCI avionics modules. Its 128-LQFP package withstands the mechanical shock and vibration of airborne and rail environments, and the -40C to +85C operating range covers the ARINC 404/600 temperature envelope. Reverse mode is particularly useful in line-replaceable units that expose a PCI bus to downstream modules.
מומלץ
FPGA-Based Embedded Platforms with Legacy PCI I/O
Xilinx and Altera SoC FPGAs typically lack a native 32-bit/66 MHz PCI host bus, so designers use the PI7C9X111SLBFDE to add PCI I/O to a PCIe-capable FPGA. The bridge exposes the full 32-bit PCI address/data bus, control signals, and arbitration lines to a standard PCI connector or to on-board PCI peripherals. Forward and reverse mode flexibility lets the FPGA act as either a PCI host or a PCI device, which is useful for prototyping and for dual-role embedded designs.
מומלץ
סיכום מוצרים מומלצים
נתוני עזר הנדסיים עבור PI7C9X111SLBFDE — השוואה, הנחיות תכנון ומידע על תאימות.
מדריך בחירה
השוואה עם חלופות
| פרמטר | מוצר זה | PI7C9X111SLBFE | PI7C9X111SLBFDEX | PI7C9X111SLAFDE | PI7C9X2G404SLBFDE | PI7C9X2G404SVAFDEEX |
|---|---|---|---|---|---|---|
| Brand | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated | Diodes Incorporated |
| Package | 128-LQFP (14x14 mm) | 128-LQFP (14x14 mm) - same | 128-LQFP (14x14 mm) - same | 128-LQFP (14x14 mm) - same | 128-LQFP (14x14 mm) - same | 128-LQFP (14x14 mm) - same |
| Function | PCIe x1 to 32-bit/66 MHz PCI reversible bridge | PCIe x1 to 32-bit/66 MHz PCI reversible bridge (tray) | PCIe x1 to 32-bit/66 MHz PCI reversible bridge (reel) | PCIe x1 to 32-bit/66 MHz PCI reversible bridge (A-grade) | PCIe Gen2 x4 packet switch (no PCI side) | PCIe Gen2 x4 packet switch, automotive |
| PCIe Generation | PCIe 1.1 (2.5 GT/s) | PCIe 1.1 (2.5 GT/s) | PCIe 1.1 (2.5 GT/s) | PCIe 1.1 (2.5 GT/s) | PCIe Gen2 (5.0 GT/s) | PCIe Gen2 (5.0 GT/s) |
| PCI Bus Support | 32-bit, 33/66 MHz | 32-bit, 33/66 MHz | 32-bit, 33/66 MHz | 32-bit, 33/66 MHz | None (PCIe switch only) | None (PCIe switch only) |
| Bridging Mode | Forward and Reverse | Forward and Reverse | Forward and Reverse | Forward and Reverse | PCIe fan-out (no bridge mode) | PCIe fan-out (no bridge mode) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | Extended automotive | -40C to +85C | Automotive extended |
| RoHS Compliance | Yes | Yes | Yes | Yes | Yes | Yes |
מבדילים עיקריים
- True forward and reverse bridging in a single chip (לעומתPI7C9X2G404SLBFDE)
- SlimLine low-power architecture (לעומתPI7C9X110BNBE)
- 66 MHz PCI bus support (לעומתEarlier PI7C9X110-series bridges)
הערות תכנון
Route the 100 MHz PCIe REFCLK+ and REFCLK- pair as a 100 ohm differential trace with length matching within 5 mils. Keep the PETp0/PETn0 and PERp0/PERn0 pairs as close to the PCIe connector as possible, with reference planes on adjacent layers. Place decoupling capacitors (0.1 uF and 1 uF) on every VDD18, VDD33, VDDA18, and VDDA33 pin, with vias placed within 50 mils of each pin to keep power-rail impedance low at the 2.5 GHz fundamental.
The 32-bit/66 MHz PCI bus generates strong edge rates that couple into adjacent traces. Maintain 3W spacing on the PCI AD[31:0] and C/BE#[3:0] bus, and keep the bus traces on a single signal layer with a continuous ground reference plane. The 66 MHz mode requires source-termination matching at the bridge side; verify signal integrity with TDR measurements on the longest AD trace to ensure the rising edge meets the PCI 2.3 spec of 1.5 ns minimum setup time.
Do not leave the M66EN, REVRSB, and TM1 straps floating. According to the Diodes PI7C9X111SL datasheet section 3.2, the bridge samples REQ_L[3:2] and REVRSB at PERST# de-assertion to configure Clock Power Management and reverse mode. A floating M66EN pin defaults to 66 MHz operation, which some downstream PCI peripherals cannot handle and may appear as a hot-plug failure during enumeration.
The PI7C9X111SLBFDE requires two independent supply rails: 1.8 V for the core and PCIe PHY, and 3.3 V for the PCI I/O and sideband signals. Power-up sequencing must satisfy VDD18 reaching 90% of nominal before VDD33 ramps, or the bridge can latch-up and draw excessive current. Add a small power-on-reset supervisor on PWRGD to ensure PERST# is not released until both rails are stable. Estimated typical power consumption is 1.2 W at 66 MHz with active PCI traffic.
מידע על תאימות
RoHS and REACH compliance per Diodes product page. Not AEC-Q100 qualified - the A-grade PI7C9X111SLAFDE variant may be selected for automotive-adjacent applications. Halogen-free status not explicitly stated in the verified data; consult Diodes for confirmation.
