EP1M350F780C5N vs EP1M350F780I5 तुलना
विस्तृत दोनों ओर की तुलना EP1M350F780C5N द्वारा Altera और EP1M350F780I5 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Altera
EP1M350F780C5N - 350K Gates Mercury FPGA w/ 1.25 Gbps CDR | Intel/Altera
EP1M350F780C5N ObsoleteAltera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 Nrndविशेषता तुलना
| पैरामीटर | EP1M350F780C5N | EP1M350F780I5 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | NRND |
| Device Family | Mercury (EP1M350) | Altera Mercury (EP1M) Enhanced Configuration Device |
| Equivalent Gates | 350,000 | — |
| Logic Cells (LEs) | 14,400 | — |
| User I/Os | 486 | — |
| Total Pins / Terminals | 780 | — |
| Logic Family | CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| Package Type | FineLine BGA (FC-FBGA / PBGA-B780) | — |
| Terminal Form | Ball | — |
| Terminal Pitch | 1.000 mm | — |
| माउंटिंग प्रकार | Surface Mount | — |
| ऑपरेटिंग तापमान | 0 C to 85 C | — |
| Transceivers | Integrated high-speed CDR to 1.25 Gbps | — |
| Architecture | LUT-based, optimized for high performance | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL rating] | — |
| फ़ंक्शन | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| पैकेज | — | 780-ball FineLine BGA (F780) |
| Temperature Grade (suffix "I") | — | Industrial |
| Speed Grade | — | 5 |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |