EP1M350F780C5N vs EP1M350F780I5 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1M350F780C5N disebabkan oleh Altera dan EP1M350F780I5 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EP1M350F780C5N - 350K Gates Mercury FPGA w/ 1.25 Gbps CDR | Intel/Altera
EP1M350F780C5N ObsoleteAltera
EP1M350F780I5 - Altera Mercury Enhanced Configuration Device, 780-pin FBGA | Intel
EP1M350F780I5 NrndPengandingan Spesifikasi
| Parametr | EP1M350F780C5N | EP1M350F780I5 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Family | Mercury (EP1M350) | Altera Mercury (EP1M) Enhanced Configuration Device |
| Equivalent Gates | 350,000 | — |
| Logic Cells (LEs) | 14,400 | — |
| User I/Os | 486 | — |
| Total Pins / Terminals | 780 | — |
| Logic Family | CMOS | — |
| Core Supply Voltage | 1.8 V | — |
| Package Type | FineLine BGA (FC-FBGA / PBGA-B780) | — |
| Terminal Form | Ball | — |
| Terminal Pitch | 1.000 mm | — |
| Jenis Pemasangan | Surface Mount | — |
| Suhu Operasi | 0 C to 85 C | — |
| Transceivers | Integrated high-speed CDR to 1.25 Gbps | — |
| Architecture | LUT-based, optimized for high performance | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL rating] | — |
| Fungsi | — | FPGA configuration PROM with integrated controller |
| Storage Density Code | — | 350 (high-density) |
| Supported Configuration Schemes | — | Passive Serial, Active Serial, Fast Passive Parallel |
| Internal Architecture | — | Configuration controller + flash memory array |
| Programming Method | — | In-system programmable via Altera Quartus / JTAG |
| Kemasan | — | 780-ball FineLine BGA (F780) |
| Temperature Grade (suffix "I") | — | Industrial |
| Speed Grade | — | 5 |
| Target FPGA Compatibility | — | Altera APEX 20K, APEX II, Mercury, Stratix-class high-density FPGAs |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Cascade / Multi-FPGA Support | — | Yes, supports daisy-chained multi-FPGA boot |
| Read-Back | — | Yes |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |