EP1M350F780I7N vs EP1M350F780C6N तुलना
विस्तृत दोनों ओर की तुलना EP1M350F780I7N द्वारा Altera और EP1M350F780C6N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ अंतिम खरीदविशेषता तुलना
| पैरामीटर | EP1M350F780I7N | EP1M350F780C6N |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Device Family | Mercury PLD (Enhanced Configuration Device) | — |
| फ़ंक्शन | Configuration device for SRAM-based LUT FPGAs | — |
| पैकेज | 780-ball FineLine BGA | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Speed Grade | 7 | — |
| ऑपरेटिंग तापमान रेंज | -40C to +100C (Industrial, I suffix) | — |
| Configuration Modes | Serial and parallel FPGA configuration | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan | — |
| On-chip Memory | Flash memory array | — |
| Configuration Controller | Integrated state-machine controller | — |
| Bitstream Support | CRC-validated, compression-compatible | — |
| माउंटिंग प्रकार | Surface Mount (BGA) | — |
| MSL स्तर | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: msl_level] |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead_free] |
| Configuration Compatibility | High-density SRAM-based LUT FPGAs (Stratix and equivalent) | — |
| Family | — | Mercury (EP1M350) |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| ऑपरेटिंग तापमान | — | 0 C to 85 C |
| Configuration Interface | — | JTAG (IEEE 1149.1) / passive serial |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |