EP1M350F780I7N vs EP1M350F780C6N Perbandingan
Perbandingan bersamaan detil EP1M350F780I7N dari Altera dan EP1M350F780C6N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EP1M350F780C6N - Mercury 350K FPGA, 486 I/O, 780-BGA | Intel (Altera)
EP1M350F780C6N ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP1M350F780I7N | EP1M350F780C6N |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Device Family | Mercury PLD (Enhanced Configuration Device) | — |
| Fungsi | Configuration device for SRAM-based LUT FPGAs | — |
| Paket | 780-ball FineLine BGA | 780-ball FC-FBGA (FINE LINE BGA-780) |
| Speed Grade | 7 | — |
| Rentang Suhu Kerja | -40C to +100C (Industrial, I suffix) | — |
| Configuration Modes | Serial and parallel FPGA configuration | — |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan | — |
| On-chip Memory | Flash memory array | — |
| Configuration Controller | Integrated state-machine controller | — |
| Bitstream Support | CRC-validated, compression-compatible | — |
| Tipe Mounting | Surface Mount (BGA) | — |
| Level MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: msl_level] |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead_free] |
| Configuration Compatibility | High-density SRAM-based LUT FPGAs (Stratix and equivalent) | — |
| Family | — | Mercury (EP1M350) |
| Device Type | — | Loadable Programmable Logic Device (PLD) / FPGA |
| Logic Family | — | CMOS, SRAM-based LUT |
| System Gates | — | 350,000 |
| Logic Cells / Elements | — | 14,400 |
| User I/Os | — | 486 |
| Integrated Transceivers | — | Yes, with CDR up to 1.25 Gbps |
| Core Supply Voltage | — | 1.8 V |
| Terminal Form | — | Ball |
| Package Code (JEDEC) | — | S-PBGA-B780 |
| Suhu Kerja | — | 0 C to 85 C |
| Configuration Interface | — | JTAG (IEEE 1149.1) / passive serial |
| Architecture | — | Look-up table (LUT)-based, optimized for high-speed serial I/O |
| Total Package Pins / Balls | — | 780 |