EP20K400GC655-3V vs EP20K400GC655-3X तुलना
विस्तृत दोनों ओर की तुलना EP20K400GC655-3V द्वारा Intel और EP20K400GC655-3X द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400GC655-3V | EP20K400GC655-3X |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Series | APEX-20KC | APEX-20KC |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Manufacturer | Altera (now Intel) | Altera (now Intel FPGA) |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | 212,992 bits |
| Typical Gate Count | 400000 | — |
| Number of User I/O | 496 | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | 714.2 MHz | — |
| Propagation Delay | 3.6 ns | — |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) | -3 (fastest) |
| पैकेज | 655-BCPGA (62.48 mm x 62.48 mm) | — |
| Package Equivalence Code | SPGA655, 47x47 | — |
| माउंटिंग प्रकार | Through Hole (CPGA) | Through-Hole (CPGA, ceramic) |
| Peak Reflow Temperature | 220 C | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Configuration | SRAM-based (requires EPC configuration device) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| ऑपरेटिंग तापमान | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| पैकेज / केस | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |