EP3SE260H780C4LG vs EP3SE260H780C3N तुलना
विस्तृत दोनों ओर की तुलना EP3SE260H780C4LG द्वारा Altera और EP3SE260H780C3N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ सक्रियविशेषता तुलना
| पैरामीटर | EP3SE260H780C4LG | EP3SE260H780C3N |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Family | Stratix III Enhanced (EP3SE) | — |
| Logic Elements | 254,400 | — |
| Adaptive Logic Modules (ALMs) | 101,760 | — |
| Embedded Memory (M9K + M144K) | 18.36 Mbits | — |
| DSP Blocks (18-bit x 18-bit) | 768 | — |
| 18-bit x 18-bit Multipliers | 1,536 | — |
| Transceivers (full-duplex) | 8 (up to 6.375 Gbps) | — |
| Maximum User I/O Pins | 488 | — |
| पैकेज | 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) | 780-BBGA, FCBGA (H780) |
| Speed Grade | C4 (commercial, mid-speed tier) | — |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Process Technology | 65 nm TSMC low-power CMOS | 40 nm CMOS |
| Operating Voltage (Core) | 0.9 V / 1.0 V / 1.1 V (programmable) | — |
| External Memory Interface | Up to 800 Mbps DDR3, QDR II+, RLDRAM II | — |
| Hard IP Blocks | PCIe Gen2, 10GbE MAC, memory controllers | — |
| RoHS स्थिति | Compliant (Pb-free HBGA) | Compliant (lead-free 'N' suffix) |
| MSL स्तर | 3 (per JEDEC J-STD-020) | — |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| ऑपरेटिंग तापमान | — | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| नमी संवेदनशीलता स्तर (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |