EP3SE260H780C4LG vs EP3SE260H780C3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C4LG sa pamamagitan ng Altera at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP3SE260H780C4LG EP3SE260H780C3N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family Stratix III Enhanced (EP3SE) —
Logic Elements 254,400 —
Adaptive Logic Modules (ALMs) 101,760 —
Embedded Memory (M9K + M144K) 18.36 Mbits —
DSP Blocks (18-bit x 18-bit) 768 —
18-bit x 18-bit Multipliers 1,536 —
Transceivers (full-duplex) 8 (up to 6.375 Gbps) —
Maximum User I/O Pins 488 —
Packhaging 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) 780-BBGA, FCBGA (H780)
Speed Grade C4 (commercial, mid-speed tier) —
Temperature Grade Commercial (0C to +85C junction) —
Process Technology 65 nm TSMC low-power CMOS 40 nm CMOS
Operating Voltage (Core) 0.9 V / 1.0 V / 1.1 V (programmable) —
External Memory Interface Up to 800 Mbps DDR3, QDR II+, RLDRAM II —
Hard IP Blocks PCIe Gen2, 10GbE MAC, memory controllers —
Tindminan RoHS Compliant (Pb-free HBGA) Compliant (lead-free 'N' suffix)
Level ng MSL 3 (per JEDEC J-STD-020) —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Series — Stratix® III E
Logic Elements (LE) — 255,000
Embedded Memory (bits) — 16,672,768
Number of LABs/CLBs — 10,200
User I/Os — 488
Number of Pins / Balls — 780
Temperature na Operasyon — 0 °C to +85 °C (C grade, commercial)
Maximum Core Frequency — [DATA_NEEDED: maximum core frequency MHz]
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
Transceivers — [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks — [DATA_NEEDED: number of DSP blocks and precision]
Level ng Sensitivity sa Asid ng Moisture (MSL) — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Configuration Method — SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

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