EP3SE260H780C4LG vs EP3SE260H780C3N 比較

詳細並排比較 EP3SE260H780C4LG 由 Altera 與 EP3SE260H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SE260H780C4LG EP3SE260H780C3N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Family Stratix III Enhanced (EP3SE) —
Logic Elements 254,400 —
Adaptive Logic Modules (ALMs) 101,760 —
Embedded Memory (M9K + M144K) 18.36 Mbits —
DSP Blocks (18-bit x 18-bit) 768 —
18-bit x 18-bit Multipliers 1,536 —
Transceivers (full-duplex) 8 (up to 6.375 Gbps) —
Maximum User I/O Pins 488 —
封裝 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) 780-BBGA, FCBGA (H780)
Speed Grade C4 (commercial, mid-speed tier) —
Temperature Grade Commercial (0C to +85C junction) —
Process Technology 65 nm TSMC low-power CMOS 40 nm CMOS
Operating Voltage (Core) 0.9 V / 1.0 V / 1.1 V (programmable) —
External Memory Interface Up to 800 Mbps DDR3, QDR II+, RLDRAM II —
Hard IP Blocks PCIe Gen2, 10GbE MAC, memory controllers —
RoHS 狀態 Compliant (Pb-free HBGA) Compliant (lead-free 'N' suffix)
MSL 等級 3 (per JEDEC J-STD-020) —
安裝類型 Surface Mount (BGA) Surface Mount
Series — Stratix® III E
Logic Elements (LE) — 255,000
Embedded Memory (bits) — 16,672,768
Number of LABs/CLBs — 10,200
User I/Os — 488
Number of Pins / Balls — 780
工作溫度 — 0 °C to +85 °C (C grade, commercial)
Maximum Core Frequency — [DATA_NEEDED: maximum core frequency MHz]
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
Transceivers — [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks — [DATA_NEEDED: number of DSP blocks and precision]
濕度敏感等級 (MSL) — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Configuration Method — SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

資料表與資源

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