EP910IDI-15 vs EP910DC-30 तुलना
विस्तृत दोनों ओर की तुलना EP910IDI-15 द्वारा Altera और EP910DC-30 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910IDI-15 | EP910DC-30 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM | — |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| पैकेज | 40-pin CDIP (CerDIP) with quartz window | DIP-40 (through-hole, 600 mil) |
| ऑपरेटिंग तापमान | -40C to +85C (industrial, "I" grade) | 0C to +70C (commercial) |
| माउंटिंग प्रकार | Through-hole (DIP) | Through-Hole |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | — |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Dedicated Inputs | — | 36 |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| सप्लाई वोल्टेज | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |