EP910LC-30 vs EP910LC-35H तुलना
विस्तृत दोनों ओर की तुलना EP910LC-30 द्वारा Altera और EP910LC-35H द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910LC-30 | EP910LC-35H |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocell Count | 24 | — |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Maximum Toggle Frequency | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS (EPROM-based) | — |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| I/O Pin Count | 24 | — |
| Dedicated Input Pins | 36 (including I/O) | — |
| Product Terms per Macrocell | Up to 16 | — |
| Programming Technology | UV-erasable EPROM cell | — |
| Development Tool | Altera MAX+PLUS II | — |
| MSL स्तर | [DATA_NEEDED: MSL level] | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | unknown |
| Family | — | Classic EPLD (EP910) |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| पैकेज | — | 40-pin Ceramic DIP (H suffix) |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| ऑपरेटिंग तापमान | — | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | — | UV (quartz window on H package) |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| क्वाइसेंट करंट | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| माउंटिंग प्रकार | — | Through-hole (Ceramic DIP) |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |