EP910LC-30 vs EP910LC-35H Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910LC-30 disebabkan oleh Altera dan EP910LC-35H disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910LC-30 | EP910LC-35H |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocell Count | 24 | — |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Maximum Toggle Frequency | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | 5 V (4.75 V to 5.25 V) |
| Process Technology | CMOS (EPROM-based) | — |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| I/O Pin Count | 24 | — |
| Dedicated Input Pins | 36 (including I/O) | — |
| Product Terms per Macrocell | Up to 16 | — |
| Programming Technology | UV-erasable EPROM cell | — |
| Development Tool | Altera MAX+PLUS II | — |
| Aras MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Family | — | Classic EPLD (EP910) |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Kemasan | — | 40-pin Ceramic DIP (H suffix) |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| Suhu Operasi | — | [DATA_NEEDED: operating temperature range grade] |
| Erasure Method | — | UV (quartz window on H package) |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Arus Dalam Tentera | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Jenis Pemasangan | — | Through-hole (Ceramic DIP) |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |