EPM5032LC-20 vs EPM5032PC-15 तुलना
विस्तृत दोनों ओर की तुलना EPM5032LC-20 द्वारा Altera और EPM5032PC-15 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5032LC-20 | EPM5032PC-15 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | 600 |
| Macrocells | 32 | — |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | 15 (15 ns tPD) |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 15 ns |
| Supply Voltage (VCC) | 5 V ±5% | — |
| ऑपरेटिंग तापमान | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | 0C to +70C (commercial) |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Inputs | 24 | — |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| पैकेज | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | 28-pin PDIP (PC suffix = windowed CerDIP) |
| माउंटिंग प्रकार | Surface Mount | Through-Hole (DIP) |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | Non-compliant (CerDIP window, contains Be) |
| MSL स्तर | [DATA_NEEDED: MSL] | — |
| Device Type | — | EPLD (Erasable PLD) |
| Macro Cells | — | 32 |
| Logic Elements / LABs | — | 1 LAB (4 macrocells per group) |
| Maximum Internal Frequency | — | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | — | 5 V (typ.) |
| Technology Node | — | 0.8 micron CMOS |
| Configuration Memory | — | UV-Erasable EPROM |
| Total Array Inputs | — | 24 |
| Pin/Package Suffix | — | PC = Windowed Ceramic DIP |
| Programming Tool | — | Altera Logic Programmer + MAX+plus II |
| Lead-Free | — | No |