EP1810JM-45 vs EP1810GM883B Perbandingan
Perbandingan bersamaan detil EP1810JM-45 dari Altera dan EP1810GM883B dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP1810JM-45 | EP1810GM883B |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Family | Classic EPLD (EP1810 series) | EP1810 (Classic EPLD) |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Technology | CMOS, UV-EPROM configuration | CMOS, UV-erasable |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | Ceramic Pin Grid Array (PGA), 84 pins |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| Jumlah Pin | 68 | — |
| Suhu Kerja | -55 C to +125 C (military grade) | -55 °C to +125 °C (Military, MIL-STD-883B) |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Tipe Mounting | Surface Mount (J-lead) | Through-hole (PGA socket or PCB through-hole) |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Status RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | — |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |