EP1810LI-35 vs EP1810LC-25 Perbandingan

Perbandingan bersamaan detil EP1810LI-35 dari Altera dan EP1810LC-25 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1810LI-35 EP1810LC-25
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Manufacturer Rochester Electronics, LLC (original Altera design) —
Part Family Altera Classic EPLD —
Device Type Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Propagation Delay (tPD) 35 ns 25 ns
Speed Grade 35 (slowest in EP1810L family) —
Paket 68-pin PLCC (J-Lead, plastic) 68-pin JLCC (J-leaded ceramic chip carrier)
Pin/Package Code PLCC-68 / PQCC68 —
Technology CMOS, UV-erasable EPROM configuration cell CMOS EPLD (erasable programmable logic device)
Tegangan Pemuat 5 V (TTL-compatible I/O) —
Suhu Kerja -40 C to +85 C (industrial, 'I' suffix) [DATA_NEEDED: temperature grade for LC package]
Tipe Mounting Surface Mount (PLCC socket compatible) Surface Mount
JTAG Boundary Scan IEEE 1149.1 compliant —
Logic Elements Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Lead-Free [DATA_NEEDED: lead-free status] —
Level MSL [DATA_NEEDED: MSL rating] —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Status Lingkungan Hidup — Obsolete (legacy Altera Classic family)

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