EP1810LI-45 vs EP1810LI-35 Perbandingan
Perbandingan bersamaan detil EP1810LI-45 dari Rochester Electronics dan EP1810LI-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ AktifPerbandingan Spesifikasi
| Parameter Umum | EP1810LI-45 | EP1810LI-35 |
|---|---|---|
| Merek | Rochester Electronics | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | CMOS, UV-erasable EPROM configuration cell |
| Tegangan Pemuat | 5 V | 5 V (TTL-compatible I/O) |
| Rentang Suhu Kerja | -40 C to +85 C (Industrial, 'I' suffix) | — |
| Paket | 68-pin PLCC / PQCC68 (J-Lead) | 68-pin PLCC (J-Lead, plastic) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Suhu Kerja | — | -40 C to +85 C (industrial, 'I' suffix) |
| Tipe Mounting | — | Surface Mount (PLCC socket compatible) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Level MSL | — | [DATA_NEEDED: MSL rating] |