EP1810LI-45 vs EP1810LI-35 比較

詳細並排比較 EP1810LI-45 由 Rochester Electronics 與 EP1810LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1810LI-45 EP1810LI-35
品牌 Rochester Electronics Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic —
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration CMOS, UV-erasable EPROM configuration cell
供應電壓 5 V 5 V (TTL-compatible I/O)
工作溫度範圍 -40 C to +85 C (Industrial, 'I' suffix) —
封裝 68-pin PLCC / PQCC68 (J-Lead) 68-pin PLCC (J-Lead, plastic)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Device Type — Erasable Programmable Logic Device (EPLD)
Propagation Delay (tPD) — 35 ns
Speed Grade — 35 (slowest in EP1810L family)
Pin/Package Code — PLCC-68 / PQCC68
工作溫度 — -40 C to +85 C (industrial, 'I' suffix)
安裝類型 — Surface Mount (PLCC socket compatible)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]
MSL 等級 — [DATA_NEEDED: MSL rating]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價