EP1830-20CFN vs EP1810LI-35 Perbandingan

Perbandingan bersamaan detil EP1830-20CFN dari Texas Instruments dan EP1810LI-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Texas Instruments
EP1830-20CFN EP1830-20CFN - 48-Macrocell CMOS EPLD, 22ns, PLCC-68 | TI

EP1830-20CFN - 48-Macrocell CMOS EPLD, 22ns, PLCC-68 | TI

EP1830-20CFN Obsolete

Perbandingan Spesifikasi

Parameter Umum EP1830-20CFN EP1810LI-35
Merek Texas Instruments Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Type Erasable Programmable Logic Device (EPLD) Erasable Programmable Logic Device (EPLD)
Technology CMOS EPROM CMOS, UV-erasable EPROM configuration cell
Macrocell Count 48 —
Propagation Delay (tPD) 22 ns 35 ns
Maximum Supply Voltage 5.25 V —
I/O Pins 48 —
Dedicated Inputs 12 —
Paket PLCC-68 (QCCJ, J-lead) 68-pin PLCC (J-Lead, plastic)
Terminal Pitch 1.27 mm —
Terminal Form J-Bend —
Package Code QCCJ —
Package Shape Square —
Operating Temperature Grade Commercial (0C to 70C) —
Typical Operating Current 20 mA at 1 MHz —
Maximum Counter Frequency 50 MHz (4 x 12-bit counters) —
Speed Grade -20 35 (slowest in EP1810L family)
Configuration Memory Non-volatile EPROM (UV-erasable) —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Manufacturer — Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Macrocells — 48
Pin/Package Code — PLCC-68 / PQCC68
Tegangan Pemuat — 5 V (TTL-compatible I/O)
Suhu Kerja — -40 C to +85 C (industrial, 'I' suffix)
Tipe Mounting — Surface Mount (PLCC socket compatible)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]
Level MSL — [DATA_NEEDED: MSL rating]

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