EP1S40B956C6N vs EP1S40F1020C5GA Perbandingan

Perbandingan bersamaan detil EP1S40B956C6N dari Intel dan EP1S40F1020C5GA dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1S40B956C6N EP1S40F1020C5GA
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Series Stratix Stratix
Family Altera Stratix (1st generation) —
Process Technology 0.13 µm CMOS —
Logic Elements (LEs) 41,250 —
Logic Array Blocks (LABs) 4,125 —
Embedded Memory 3,423,744 bits (~3.4 Mbit) —
Maximum User I/O 683 —
Tegangan Pemuat 1.425 V to 1.575 V (1.5 V nominal) —
Suhu Kerja 0 °C to +85 °C (Commercial) 0C to +85C (Commercial)
Paket 956-ball FineLine BGA (FCBGA) 1020-BBGA (FineLine BGA)
Package Dimensions 40 mm x 40 mm —
Ball Pitch 1.27 mm —
Speed Grade C6 (commercial, mid-speed) C5
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Active Serial —
Tipe Mounting Surface Mount Surface Mount
Level MSL [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
Status RoHS [DATA_NEEDED: RoHS compliance] Unknown - non-GA suffix commercial part
Logic Elements (LE) — 41,250
Total RAM Bits — 3,423,744
User I/O Count — 773
Process Node — 0.13 µm CMOS with 9-layer metal
Supply Voltage (Core) — [DATA_NEEDED: VCCINT value]
I/O Bank Count — [DATA_NEEDED: bank count]
DSP Blocks — Embedded multiplier blocks (count per Stratix datasheet family)
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
Lead-Free — Yes (per Altera/Intel policy at release)

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