EP2A25F672C7N vs EP2A25F672I6 Perbandingan

Perbandingan bersamaan detil EP2A25F672C7N dari Altera dan EP2A25F672I6 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP2A25F672C7N EP2A25F672I6
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family APEX II APEX II
Logic Elements 24,320 cells —
System Gates Approximately 900,000 —
User I/Os 492 —
Propagation Delay (tPD) 1.69 ns —
Internal Operating Frequency Up to 500 MHz —
Core Voltage (VCCINT) 1.5 V —
Process Technology 0.15 µm all-layer copper (up to 8 metal layers) 0.18 µm CMOS
Logic Family CMOS —
Package Type 672-ball FC-FBGA (FineLine BGA) —
Package Body Size 27 x 27 mm —
Ball Pitch 1.0 mm —
Suhu Kerja 0 °C to 85 °C (commercial) —
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps —
Programmable Logic Type Loadable PLD (in-system programmable) —
Embedded Memory Embedded System Blocks (ESB) configurable as dual-port RAM/ROM Embedded System Blocks (ESB), dual-port RAM / CAM
PLLs Up to 4 —
Tipe Mounting Surface Mount Surface Mount (BGA)
Status RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
Paket — 672-ball FineLine BGA (FBGA-672)
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Temperature Grade — Industrial (-40 °C to +100 °C ambient)
Speed Grade — 6
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
Level MSL — [DATA_NEEDED: moisture sensitivity level]

Spek dan Sumber

Buka Semua Produk Buat BOM Ajukan Diskon