EP610DC-35 vs EP610DI-35 Perbandingan

Perbandingan bersamaan detil EP610DC-35 dari Altera dan EP610DI-35 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP610DC-35 EP610DI-35
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Device Type CPLD - Classic EPLD —
Family Altera Classic EP610 Altera Classic EPLD
Macrocells 16 —
Usable Gates 300 300
Propagation Delay (tPD) 35 ns —
Maximum Frequency (fMAX) 28.6 MHz —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V —
Process Technology CMOS —
Program/erase Method UV-erasable (windowed CERDIP) —
Paket 24-pin CDIP (windowed CERDIP) 0.300 inch 24-pin CDIP (Ceramic DIP)
Tipe Mounting Through-Hole (DIP) Through-hole
Suhu Kerja 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] [DATA_NEEDED: industrial/commercial grade range]
Manufacturer Originally Altera; today supplied via Rochester Electronics (authorized) —
Status RoHS [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] [DATA_NEEDED: not confirmed in supplied web data]
Series — EP610
Logic Cells / Macrocells — 16 macrocells
Product Terms — 160
I/O Pins — 16 bidirectional
Total Inputs — 20 (including 4 dedicated inputs)
Propagation Delay (tpd) — 35 ns
Maximum Toggle Frequency — 28.6 MHz
Internal Pipelined Data Rate — Up to 100 MHz
Tegangan Pemuat — 5 V
Technology — CMOS, UV-erasable

Spek dan Sumber

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