EP610ILC-25 vs EP610DC-35 Perbandingan
Perbandingan bersamaan detil EP610ILC-25 dari Altera dan EP610DC-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP610ILC-25 | EP610DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | Altera Classic EP610 |
| Device Type | EEPLD (Electrically Erasable PLD) | CPLD - Classic EPLD |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| Rentang Suhu Kerja | 0 C to +70 C (commercial) | — |
| Paket | 28-pin PLCC (J-lead) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Tipe Mounting | Surface Mount | Through-Hole (DIP) |
| Process Technology | CMOS, electrically erasable | CMOS |
| Programming Method | In-system, electrically erasable | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Suhu Kerja | — | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |