EP610ILC-25 vs EP610DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-25 sa pamamagitan ng Altera at EP610DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC-25 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD (EP610 series) | Altera Classic EP610 |
| Device Type | EEPLD (Electrically Erasable PLD) | CPLD - Classic EPLD |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| Hanay ng Temperature na Operasyon | 0 C to +70 C (commercial) | — |
| Packhaging | 28-pin PLCC (J-lead) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Uri ng Pagpapasok | Surface Mount | Through-Hole (DIP) |
| Process Technology | CMOS, electrically erasable | CMOS |
| Programming Method | In-system, electrically erasable | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Temperature na Operasyon | — | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |