EP610JI-30 vs EP610ILC-10 Perbandingan

Perbandingan bersamaan detil EP610JI-30 dari Altera dan EP610ILC-10 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP610JI-30 EP610ILC-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family Altera Classic EPLD (EP610) —
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz —
Product Terms 160 160
Dedicated Inputs 4 4
I/O Pins 16 16
External Clocks 2 —
Tegangan Pemuat 5 V (single supply) 5 V (single supply)
Process Technology CMOS —
Paket CQCC28 (windowed ceramic JLCC, J-bend) PLCC-28 (plastic J-lead chip carrier)
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Suhu Kerja -40C to +85C (industrial, per EP610 family suffix convention) [DATA_NEEDED: operating temperature range]
Tipe Mounting Surface Mount (JLCC) Surface Mount (PLCC socket or solder)
Status RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — Classic EPLD
Product Type — UV-Erasable / OTP PLD
Architecture — PAL-type with macrocells
Usable Gates — 300
Pin-to-Pin Delay (tPD) — 10 ns (grade -10)
Counter Frequency (fCNT) — 100 MHz
Logic Family Compatibility — TTL (5 V CMOS/TTL-compatible I/O)

Spek dan Sumber

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