EPC16QC100N vs EPC16QI100TBAC Perbandingan
Perbandingan bersamaan detil EPC16QC100N dari Altera dan EPC16QI100TBAC dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPC16QI100TBAC - Altera Enhanced Configuration PROM 16Mb | FPGA
EPC16QI100TBAC ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EPC16QC100N | EPC16QI100TBAC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Ukuran Memori | 16 Mbit (16,777,216 bits) | — |
| Programmable Type | In System Programmable | — |
| Configuration Clock Frequency | 33 MHz max | — |
| On-Chip Decompression | Yes (supports compressed bitstreams) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Access Time | 90 ns typical | — |
| Flash Read Bandwidth | 160 Mbps (16-bit DQ at 10 MHz) | — |
| Configuration Interface | FPP / PS / AS via dedicated FPGA pins | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Suhu Kerja | 0 C to 70 C | -40C to +85C (industrial) |
| Paket | 100-pin PQFP (20 x 14 mm) | 100-pin PQFP (20 x 14 mm) |
| Tipe Mounting | Surface Mount | Surface Mount (PQFP) |
| Lead Free | Yes (per datasheet) | — |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | Altera Stratix, Cyclone, Arria series |
| Memory Density | — | 16 Mbit (2 Mbyte) |
| Tipe Memori | — | Flash (Enhanced Configuration Device) |
| Tegangan Pemuat | — | 3.3 V |
| Configuration Modes | — | Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), Passive Serial (PS) |
| Maximum Configuration Clock | — | 40 MHz |
| Number of Configuration Pages | — | Up to 8 (selectable via PGM[2..0]) |
| In-System Programmable | — | Yes (via JTAG / IEEE 1149.1) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan and programming) |
| Data Compression | — | Supported (15-30% density gain depending on target FPGA) |
| Level MSL | — | 3 (168 hours) |
| Lead-Free / RoHS | — | Lead-free (per JEDEC J-STD-020); RoHS compliance: [DATA_NEEDED] |
| Dynamic Reconfiguration | — | Yes (page mode via PGM[2..0] pins) |
| Configuration Controller | — | Integrated |
| Programming Interface | — | JTAG / 4-wire passive serial |