EPC1LC20-W vs EPC1L20 Perbandingan

Perbandingan bersamaan detil EPC1LC20-W dari Altera dan EPC1L20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC1LC20-W EPC1L20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup Obsolete Aktif
Tipe Memori OTP (One-Time Programmable) Configuration PROM OTP Configuration PROM (Flash)
Ukuran Memori 1 Mbit 1 Mbit
Configuration Clock (DCLK) 8 MHz maximum —
Tegangan Pemuat 3.3 V and 5.0 V 3.3 V (typical)
Antarmuka Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) Serial / FPP configuration + JTAG (IEEE 1149.1)
In-System Programming Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V —
Paket 20-PLCC J-lead (9x9 mm) 20-pin PLCC (9x9 mm)
Lead Finish Pb-free (matte tin) - "-W" suffix —
Daisy-Chain Support Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs —
Compression Support Yes - stores compressed Altera FPGA bitstreams —
Rentang Suhu Kerja [DATA_NEEDED: operating temperature range] —
Programming Cycles 1 (OTP) —
Target FPGA Families Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury —
Status RoHS Compliant (Pb-free -W finish) [DATA_NEEDED: RoHS compliance]
Tipe Mounting Surface Mount (PLCC socket or direct solder) Through-Hole / Socket
Configuration Clock (max) — 8 MHz
Flash Access Time — 90 ns (approx.)
Max Read Bandwidth — 160 Mbps (16-bit DQ bus)
Programmability — One-Time Programmable (OTP)
Suhu Kerja — [DATA_NEEDED: operating temperature range]
JTAG / ISP Support — Yes (IEEE 1149.1)
Compatible FPGA Series — Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families
Lead-Free — [DATA_NEEDED: lead-free status]

Spek dan Sumber

Buka Semua Produk Buat BOM Ajukan Diskon