EPC1LC20-W vs EPC1L20 比較

詳細並排比較 EPC1LC20-W 由 Altera 與 EPC1L20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC1LC20-W EPC1L20
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete 啟用中
記憶體類型 OTP (One-Time Programmable) Configuration PROM OTP Configuration PROM (Flash)
記憶體容量 1 Mbit 1 Mbit
Configuration Clock (DCLK) 8 MHz maximum —
供應電壓 3.3 V and 5.0 V 3.3 V (typical)
介面 Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) Serial / FPP configuration + JTAG (IEEE 1149.1)
In-System Programming Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V —
封裝 20-PLCC J-lead (9x9 mm) 20-pin PLCC (9x9 mm)
Lead Finish Pb-free (matte tin) - "-W" suffix —
Daisy-Chain Support Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs —
Compression Support Yes - stores compressed Altera FPGA bitstreams —
工作溫度範圍 [DATA_NEEDED: operating temperature range] —
Programming Cycles 1 (OTP) —
Target FPGA Families Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury —
RoHS 狀態 Compliant (Pb-free -W finish) [DATA_NEEDED: RoHS compliance]
安裝類型 Surface Mount (PLCC socket or direct solder) Through-Hole / Socket
Configuration Clock (max) — 8 MHz
Flash Access Time — 90 ns (approx.)
Max Read Bandwidth — 160 Mbps (16-bit DQ bus)
Programmability — One-Time Programmable (OTP)
工作溫度 — [DATA_NEEDED: operating temperature range]
JTAG / ISP Support — Yes (IEEE 1149.1)
Compatible FPGA Series — Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

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