EPC1LC20-W vs EPC1L20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC1LC20-W sa pamamagitan ng Altera at EPC1L20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC1LC20-W EPC1L20
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Aktibo
Uri ng Memory OTP (One-Time Programmable) Configuration PROM OTP Configuration PROM (Flash)
Laki ng Memory 1 Mbit 1 Mbit
Configuration Clock (DCLK) 8 MHz maximum —
Volte ng Pagbibigay 3.3 V and 5.0 V 3.3 V (typical)
Interface Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) Serial / FPP configuration + JTAG (IEEE 1149.1)
In-System Programming Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V —
Packhaging 20-PLCC J-lead (9x9 mm) 20-pin PLCC (9x9 mm)
Lead Finish Pb-free (matte tin) - "-W" suffix —
Daisy-Chain Support Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs —
Compression Support Yes - stores compressed Altera FPGA bitstreams —
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Programming Cycles 1 (OTP) —
Target FPGA Families Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury —
Tindminan RoHS Compliant (Pb-free -W finish) [DATA_NEEDED: RoHS compliance]
Uri ng Pagpapasok Surface Mount (PLCC socket or direct solder) Through-Hole / Socket
Configuration Clock (max) — 8 MHz
Flash Access Time — 90 ns (approx.)
Max Read Bandwidth — 160 Mbps (16-bit DQ bus)
Programmability — One-Time Programmable (OTP)
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
JTAG / ISP Support — Yes (IEEE 1149.1)
Compatible FPGA Series — Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families
Lead-Free — [DATA_NEEDED: lead-free status]

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