EPC2LS20U vs EPC2L20 Perbandingan

Perbandingan bersamaan detil EPC2LS20U dari Altera dan EPC2L20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2LS20U EPC2L20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup Obsolete Obsolete
Product Type In-System Programmable Configuration PROM —
Memory Density 1.6 Mbit —
Operating Voltage (VCC) 3.3 V —
Antarmuka Altera serial configuration / JTAG Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532)
Programming Method In-System Programmable (ISP) via JTAG —
Paket 20-PLCC (J-lead, 9x9 mm) 20-pin PLCC (J-lead)
Lead-Free / RoHS Yes (per "U" suffix) —
Suhu Kerja [DATA_NEEDED: Operating Temperature] [DATA_NEEDED: operating temperature range]
Supported FPGA Families Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 —
Configuration Modes PS (Passive Serial), AS, FPP —
JTAG Support Yes (IEEE 1149.1 boundary scan) —
Done Pin Yes (open-drain programmable polarity) —
nSTATUS Pin Yes (open-drain error flag) —
nCONFIG Pin Yes (reset/reconfiguration input) —
DCLK Output Yes (configuration clock to FPGA) —
Level MSL [DATA_NEEDED: MSL Level] [DATA_NEEDED: MSL rating]
Compliance RoHS (Pb-free per U suffix) —
Tipe Memori — Configuration PROM (non-volatile)
Ukuran Memori — 1.6 Mbit
Organisasi — 8-bit byte
Programmability — In-system programmable via JTAG
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 5.0 V (VCCSEL selectable)
Cascade Support — Yes - multi-device daisy chain
Boundary Scan — JTAG IEEE 1149.1 BST
Tipe Mounting — Surface Mount (PLCC socket compatible)
Status RoHS — RoHS Compliant (per IC Components listing)
Process Technology — Low-power CMOS
Target FPGAs — APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix

Spek dan Sumber

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