EPM3256AFC256-10N vs EPM3256AFC256-10 Perbandingan
Perbandingan bersamaan detil EPM3256AFC256-10N dari Altera dan EPM3256AFC256-10 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EPM3256AFC256-10N | EPM3256AFC256-10 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 gates | 5,000 |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Paket | 256-pin FineLine BGA | 256-ball FBGA (Fine-Line BGA) |
| Logic Family | CMOS | CMOS (EEPROM-based) |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| Suhu Kerja | 0 C to 70 C (commercial) | 0°C to +70°C (Commercial) |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 (16 macrocells each) |
| Maximum User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| In-System Programmability | — | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |
| Tipe Mounting | — | Surface Mount |
| Status RoHS | — | [DATA_NEEDED: RoHS compliance status] |