EPM3256AFC256-10N vs EPM3256AFC256-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-10N sa pamamagitan ng Altera at EPM3256AFC256-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256AFC256-10N EPM3256AFC256-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 5,000 gates 5,000
Macrocells 256 —
Maximum User I/O 161 —
Pin-to-Pin Logic Delay 10 ns —
Maximum Counter Frequency 227.3 MHz —
Core Voltage 3.3 V —
I/O Logic Level Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Programmability EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) —
Packhaging 256-pin FineLine BGA 256-ball FBGA (Fine-Line BGA)
Logic Family CMOS CMOS (EEPROM-based)
PCI Compliance PCI Local Bus Specification Rev 2.2 (at -10 grade) —
Temperature na Operasyon 0 C to 70 C (commercial) 0°C to +70°C (Commercial)
Macro Cells — 256
Logic Array Blocks (LABs) — 16 (16 macrocells each)
Maximum User I/Os — 161
Propagation Delay (tPD) — 10 ns
Internal Counter Frequency (fCNT) — 95.2 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage Tolerance — 5.0 V tolerant
In-System Programmability — Yes (3.3 V ISP via JTAG IEEE 1149.1)
Pitch — [DATA_NEEDED: BGA ball pitch]
Uri ng Pagpapasok — Surface Mount
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]

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